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107 Threads found on edaboard.com: Fpga Constraints
Another suggestion I have been given is to add constraints into the design (which will help fix the design and avoid the timing issues). When we've tried this, the build time goes from 2-3 mins to 20+ mins making it very inconvenient. Perhaps this is a sign we are doing something wrong? The build time issue occurs even if I ad
The design requirement is to pass these signals through the fpga without any logic or registers involved and maintain the same timing relation. IN this scenario, I wouldn't put any constraints in the SDC file. So, what would you do to keep the same timing relationship between the signals? If you are not doing anythi
Hi All, I am using Virtex 7 1157 fpga. My design with RTL is freezes. I cannot modify a single line in the RTL. I needs to infer the DSP blocks for particular adder logic in my design. During the Synplify synthesis, I observed that automatically these adder are not using DSP blocks. Is there any *.sdc constraints for inferring the DSP block
@anubudihal, that is the last step.... You'll first have to synthesize the code, then place and route based on your input constraints, generate a programming file, then use the programming cable. Maybe you should read the documentation of the fpga vendors tool flow instead of asking a vague question that just proves you never even tr
Hello, I am working with ISE 14.7 targeting a Virtex-5 fpga. I manually placed and routed some components of my design. I know that those new constraints (PLACE&ROUTE) are written automatically in PCF file. But I am wondering to know how can I export the manual routing and placement constraints from fpga Editor to the (...)
1. First of all post it in the correct forum (PLD, SPLD, GAL, CPLD, fpga Design)! 2. There are many {} in the xdc command, which one is needed? 3. Have you referred to the Xilinx constraints manual, UG903.pdf where most explanations are present?
Could you be more specific? Do you want a digital circuit? An analog circuit? Any constraints? Frequency? A simple 555 timer would do this. So could an fpga.
fpga synthesis tools have timing analysis to check if a design is able to run at the intended clock frequency and usually also implement timing driven synthesis to tune the design for maximum speed if required. So the first step would be to write suitable timing constraints and determine the achievable counter speed. Not knowing the used CPLD, i
Hello all, I am confused about putting the input setup in fpga and I am new to timing constraints issues. let say I have the following: 1. clka = 50Mhz is coming from outside the fpga 2. data in/out with the same clokc rate, do you know how can select my setup time? if I put pll-asic and there is a delay by -2ns what should be (...)
It could also be considered an over-constrained constraint. In the past for ASIC tools and currently in most fpga tools. If you over-constrain with a near impossible or impossible constraint the tools would either a) give up and give you whatever the last pass result was (good or bad) or b) spend a ridiculous amount of time then give you something
Hello, I have a very high speed design implemented into Virtex-5 fpga operating at 500MHz. I am using ISE14.7. The design is fully placed and routed with no errors and warnings ! Also, the post place&route simulation results are great. Now, I am looking a way how to assure that this design works properly in reality while it is implemented into t
Hello Everyone, I have implemented a circuit of fpga using Xilinx ISE Design Suite. Now I want to calculate following parameter. 1) Maximum Frequency 2) Minimum Available Offset In 3) Minimum Available Offset Out How to calculate above parameter? Need Help. Thanks.
ZYNQ is SoC (system on chip). Aside PL (fpga fabric) there is also uController (CPU and some peripherals). Among those uController peripherals there are 2x I2C (master or slave) controllers ready to use. You don't need to do any fpga time constraint for uController peripherals, you just connect their pins via MIO or EMIO to outside chips. If you us
Hi all, I have a doubt related to clock uncertainty in the fpga design flow using (for example) Quartus. Why should someone want to overwrite the clock uncertainty generated by "derive_clock_uncertainty" using the "set_clock_uncertainty"? Isn't the derived uncertainty enough precise to be trusted by the designer? Thanks in advance
Depends on a lot of factors. Whether you are synthesizing a design for an ASIC or fpga, what are your requirements. I had synth. a microprocessor design to be implemented on a fpga using only the create_clock constrain, nothing else.
Hello, After synth. of a simple SoC design using Synplify for a Xilinx Spartan6 target, I used Xilinx ISE suite to run the PnR process. I had a lot of setup violations (for the sdc constraints I have used) but all the processes involved in the PnR completed successfully. Finally I had the .bit file for the fpga generated. Can I use this .bit
I am doing CDC on fpga. Even for ASIC, if we are doing CDC using STA tool, how do we do it? We should be indicating the crossing path as false path through clock grouping asynchronous option isnt it? or do we give some other constraints to indicate CDC in ASIC?
I am trying to interface a Freescale microcontroller (MPC) with fpga. MPC has an external bus interface (EBI) with EBI clock (CLKOUT) which can be used by the fpga. All control/address/data signals of MPC (TS, TA, CS, RDWR, ADDR, DATA etc.) are output by MPC wrt the CLKOUT signal. The fpga is sampling the MPC control/address/data signals (...)
HI All! Im a beginner in this forum and currently studying as a MS student. Im studying Cadence COnformal tool to check the equivalence of RTL to gate-level netlist. Now I've done the latter. My question is that is there any possible way to check the formal equivalence of a gate-level netlist or (RTL netlist) versus FULL CHip fpga netlist?
The document from altera gives a mathematics equation for minimum and maximum input and output delays when am fpga is connected to an external device. In the figures 7-12 and 7-14, the term cd_altr which clock insertion delay for the fpga is and cd_ext which is clock insertion de