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Hi, I am the maker of UltraMiner fpga, I?d like to introduce you to our project, which will be launched on CrowdSupply platform soon! (please sign up for project update if interested!) Our fpga board is designed with the latest Xilinx 16nm UltraScale+ Kintex, very high performance and p
Dear friends, So far one of our mentors, Panch told me about excellent source to simulate the fully differential amplifier using Balun, I am using now this instance and giving me good shorcut. One issue I have with simulating the common mode gain (ACM), attached you see the setup according to the source explanation 155577[/A
Are you discussing an fpga design with embedded software to run the fpga design (Cyclone V DE1-SoC) or a software solution on a Raspberry Pi 3? If you are only using the Cyclone V's dual core A9 then this question doesn't even belong in the fpga section. As you are considering a Pi3 instead of the SoC solution then you probably had no (...)
hi , in my current project , i am facing an error regarding site rows . it says site rows are overlapping. can anyone guide me how to resolve this error . Regards
Hi guys, I want to build a new EMF meter but EMF meters are limited they can work around 60 hz, they can detect wider range but still not enough for me, so I wanted to change my direction and build a power meter for all range detection. Which diode is good for all bands or which kind of circuit? Any suggestions?
Hi, I have custom fpga board which has a lot of peripherals like: temperature sensors, RTC, ADC etc. The board has also a high speed mezzanine connector to communicate and take data from some high- speed ADCs and not only. Right now I am thinking to design the firmware in term of the length of the data string which will be send out from the F
I have few clarifications on the MCLV-2 board software and the schematics. I have attached the source code of AN2520 application noted, schematics of the board and AN1292 application note. Q1. Referring to the userparams.h file // Following parameters for MCLV-2 board // Gain of opamp = 15 // shunt resistor = 0.025 ohms // DC offset =
Hello all my post readers, I am very new to fpga, a weak ago started playing with a spartan 6. (Papilio pro). Now connected a 320x240 LCD to it and planning to do something with that as a hello world. I have a decent experience on electronics hardware, digital circuits and embedded firmware development. But first time with fpga. Learning VHDL no
hey guys I have designed a custom board with a fpga. when I do initialize chain in iMPACT I recevice this message: Attempting to identify devices in the boundary-scan chain configuration... INFO:iMPACT - Current time: 9/28/2019 5:34:02 PM PROGRESS_START - Starting Operation. Identifying chain contents...INFO:iMPACT:1588 - '0':The part
Hello everyone, I doubt the simulation when I go to Choose EM> Post-Processing> Far Field to open the Far Field Computation Setup dialog box. .... This message appears I do not know what to do, please need guidance. Current or Field information required for far field computation is not available. Set the option 'Save currents for' to 'User
I want to implement a digital filter and tuned amplifier for (39 KHz and 50 kHz) in DSP. Currently the whole implementation of filtering transients and noise and tuned amplifier is in Analog and I would like to implement everything using DSP with excellent noise immunity. As the circuit gets its input from the wheel sensor mounted at the tracks
Normally priced at 300GBP, this is the completely unlimited version of one of the most widely used DSP applications. This release of ONEoverT with no restrictions, may be used to design FIR, IIR, Raised Cosine, Hilbert Transforms and a range of other filters. It is being offered at a special discount price of 40 GBP to help students and hobbiests
Hi everyone, I have a queation about convergence criteria, described in The Designer's guide to Spice and Spectre (by Ken Kundert) In the book on page 20, It is stated that "The first criterion specifies that KCL should be satistied to a given degree, |fn(vk)|
you need a flash device,and connect to your fpga board. An oscilloscope maybe also need.
Hi guys, I was looking for some ideas to decide my fyp tittle on google and I found this forum. So I register and hope to get some suggestion. As far as I know fyp is the project that modify others' fyp? I am not so sure because I really have no any idea, But I do know I am interested in fpga things. And maybe its fun to combine fpga with netwo
Hi I have a Evaluation Board TX7316 for Ultrasound signals. I am running it in 3 level mode. It can be run in on chip or off chip mode. When i run it on chip it has limitations in terms of number of transitions possible for the pulses i.e. Maximum number of transitions per pattern profile for 3-level is 16(Table 4). That means it cannot jump be
Dear all, I am trying to model analog latch in verilog-a but have been unable to do it. The requirement is as follows It is required to sample an analog value at positive clock cycle of CLK2 and hold the same value even during the negative clock cycle of CLK2. Any leads??
I was debugging the MP1584 module, 5v regulator circuit in the PCB. I have attached my debug circuit below. 155403 I have completed my circuit in breadboard and PCB also, but I was connected to any load below 2A. It will produce the voltage drop and alternative output voltage. Mp1584 specs : max 3A , i/p volt =
Hello, I want to measure the INL/DNL of an ADC designed in Cadence Spectre/Virtuoso. I understand the methodology: apply an ideal DAC at the output, apply a ramp signal, or a sine wave and get the output and generate a histogram of the output codes. My question is: how to I generate a histogram of the output codes - that is - a plot of the
Hi, I need a pi filter, but the this topology is very rare. Is it possibility to do it? Is it accidental?