Search Engine

Fpga Guide

Add Question

1000 Threads found on Fpga Guide
For , how to derive expression (14) ?
Hello all, I posted a similar question on xilinx forum, however I know this forum and community is much more informative and responsive. The goal it to create a configurable gpio pad ring for an fpga design. A package file contains the information for GPIO_TC_DIR and GPIO_TC_TYPE, which are the conditions used in a generate statement to determi
Hello. I think this is a property forum.This is a thing, which I think about it more often. Viz, what skills from electronics/electrical engineers are more and more desirable? Well, my favorites thing about electronics are analog design, optics and and RF engineering, and I am doing it at big company since few years, and I like it. But are they a
Hi, I need some help in designing this crystal oscillator circuit. I have attached the diagram. I want it to oscillate around 1MHZ. How do i calculate the capacitor and resistor values values? Can you please share the formulas
Hello, I would like to ask: How to generate differential (two lines) clock from "normal" clock (one line). The clock frequency is 100 MHz. Project is written in Verilog and I am using "ISE Webpack 14.7" (Windows10 Pro) for synthessis. My fpga is Spartan6 (XC6SLX9 in CSG324 package) on Mimas V.2 board (Numato). Thanks in advance and Regards
Hello there, I'm looking for detail information on Core I3-350M Intel processor ... For some reason I cannot find detail specification for Core I3 1st generation. /on Intel site/ Please help!
Hi, i want to find board with Intel fpga and ADC more that 1 GSPS sample rate. I found on a lot of sites, but my bad knowledge in english let me find only 1 example (3DR-A10-ADC-10GSPS). But i want to find 5-6 examples for my graduate work. please help me. or advise me, how should i find this boards in google or any another sites
Hello, I was implementing a 5 bit DAC to be used in a CT sigma delta modulator. I would like to model the error due to clk Jitter at the output of the DAC in VerilogA. Any Ideas?
I agree with std_match, there's a potential simulation mismatch with this code, as discussed in previous Edaboard threads, e.g. Hardware synthesis can be expected to follow the known register template and creates asynchronous set and reset function with
Am totally new to electronics and the datasheet is very confusing to me, so can anyone please guide me through the specification of the accelerometer? So that i can have a better understanding on the accelerometer and to be able to convert the accelerometer data into G. X-axis Y-axis Z-axis -28 -26 218 These are the readings i get from the accel
Hi, I am using pic24hj128gp502 I am generating a 1KHz signal using a function generator, 5Vpk-pk, 20% duty. I need to measure the PWM usnig my PIC24 and see it in my UART2 port. I have executed UART2 port and I can see a message that i send I saw some guide regarding input capture compare but I didn't understand how to implement it
I have 21 year old .PCB file. Looking to convert this to ASCII format that I can then read into a different software tool. For example for latest CADSTAR would be a .PAF file. Looking to convert file to format like ODB++, GenCad etc. Will be devleloping test for the board design and not doing any design. Inside file using notepad see the f
I am an experienced chip designer with more than 8 years of design career. I am particularly specialized in fpga, DSP and RF design and I am also skilled at designing mixed analog and digital circuits. Since 2009 I entered into the VLSI industry and have designed numerous chips in various industry fields for a number of clients. Design of Modem
Hi, I have created a MIF file containing 100 x 16bit values. The values point to a colour palette which contains the RGB values for 10 colours. In Quartus Prime Lite I have used the IP Catalogue to create a ROM: 1-Port file My top Verilog HDL file references the ROM file which when compiled / simulated on the fpga development board should
Hi, how to implement link training with IO DELAY in Xilinx ultrascale fpga? Any idea or reference design? Thanks
Hello Dears Signal coming from raspberry and i check this by divide clk and send to leds. and also can output to monitor hdmi in use Mike Fiels projects. But smth strange and i cannot deliver signal from raspberry to monitor make just pipe from fpga Virtex4. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.A
Hello, Is there a formula to estimate how much time does a neural network need for training? I am trying to build a CNN for image processing, 640x480 images on Virtex 5 (without success however...). I have read articles about that, but I haven't seen anywhere talking about training time. Thank you...
i have an input signal which goes active state (high or low) for 1usec and remain idle state (low or high) for the rest of the time ... i want to put a delay in its active 1usec pulse . such that output has 2usec active state . i dont want to use microcontroller here , just want to achieve this with some electronics circuit. Please guide? (t
Hi all I am working on beam forming of high frequency (>400 KHz) linear array for imaging sonar. I have gathered sensor data of 80 channel linear array sub merged halfway in 8 m deep water tank with a transmitting probe 6 m away from it at same depth. I recorded multiple pulses and perform offline analysis on it. The problem i am facing is very
This looks like you converted a c program directly to vhd. And then created a testbench with a ridiculous 60GHz clock. Did you create a circuit diagram before you wrote the code,? This code is unlikely to work at any reasonable speed (a few mhz if you're lucky) in a real fpga. As to why it's crashing, have tot tried 2018.3? If that still crashe