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Hello, My goal is to find out how to synthesis and place&routing is affected after small modifications to an existing VHDL code. After a small change (e.g. halving the threshold frequency) in a bigger structure, I have to make sure that the not changed parts of the code post P&R should stay the same and be equivalent, so that I don't have to ve
Dea Forum Im designing a FIR filter, in this case a low pass. I get the coefficients from Matlab (no matter from where..) ,that are from 0 to 1, in floating point. Now, I want to implement this FIR in my fpga ,with buil in 18x18 multiplier. So,I transform the coefficient in integer value of max 17 bit (1 bit for sign) ,multipling (...)
I have question How can we send multiple bytes via UART?, What happen if we want to send multiple bytes assume want to send 8 bytes ? If I want to send one byte data, I can send like : start-byte1-stop //send one byte Can we send like this start -> byte1-byte2-byte3-byte4-byte5-byte6-byte7-byte8-stop //
Hi, I am working with a project having around 70 DDR LVDS 910 Mbps connections to fpga. I am wondering if ZYNQ 7Z030 have enough LVDS IOs with at least 910 Mbps ? Another question, as there are two Ethernet Controllers in ZYNQ 7Z030, does this means that no Ethernet controller chip is required on the PCB and only Ethernet PHY port is needed
Hi I want to combine 8 loop antennas into one structure, each of them at a different angle to the others. By using 8 relays, I want to select each of these 8 loops so that I can null a signal at a wanted direction. So instead of using a single loop and a rotor, to use multiple loops and select each of them. Now the problem I have is that I have on
I can speak about the fpga tools, specifically Vivado. They don't have capabilities of an automatic wrapper creation. You must write the RTL for it.
This is second part of my post: I am a bit confused because this is soft-core with status stable and was checked earlier. Maybe reason of such many warnings is caused that it is old design (as far as I can see the project was made with Xilinx ISE10), The project also had some parts based on Xilinx Virtex fpga and is hardware dependend. See sc
If you are doing a 300W LED bank comprising say ten COB LEDs. You will want a certain light area distribution, and would use lenses to get this. The thing is, do you make one lens giving the required light distribution and use that same lens on all ten LEDs?or?is it better to make several different lenses , each pointing in a different direction,
Hi, can anyone recommend an EVN or stacked fpga system for capturing a still image? preferred 720p. I would like to trigger a snapshot - freeze the video and transfer the image via USB to a PC (via FTDI or Cypress USB chipset). The picture should only be transferred once the trigger occurred. This would be my first application with a camera
Hi I will be working on my amplifiers, some of which are PCB, and some of which are PTP. Currently, I have a basic Weller. It works, but I wonder if I should get something better, maybe one that has variable temp? If so, what is a good one to get? And is there a general rule for temps when desoldering and soldering components from and to a
Hi all, After reading many posts in the forum, I started to get confused. My understanding on metastability is it cause the output to be X. This mean it can be any values. By having high MTBF, we have high probability to avoid metastability. My question is does this mean we will have a correct output value? Or it just won't be intermediate va
I'm looking for old Altera EPM7128SL fpgas. On ebay there are many at a bargain price, but I don't trust them. Could you give me some advice on where to buy them?
Hello, i agree with @KlausST. If you are looking for theoretical information see links to these
Hello, I am looking for best way (in sense of speed and simplicity) how to connect STM32 MCU to fpga board (Artix-7). The comunication must be two-directional. I am experimenting with some kind of coprocessor for ARM CortexM4 core. The MCU is sending data to process for fpga and after fpga ended processing is receiving processed data. I (...)
Hi All, am appealing to anybody who has a similar environment to give me a few tips here :) The internet problem is weird, the system default is ffox 70 that runs fine standalone but none of the quartus menu's that would invoke it (help etc) work you just get no response. The same is true even if you set the browser path directly to ffox instead
Moreover your country could levy import taxes on electronic products (when the amount crosses a certain limit). So check that out. (If I buy an fpga board from Digilent USA and make it ship to Germany, I have to pay some euros extra as tax, which I don't need to pay if I buy the same board from Digilent German website).
I think we've had this discussion before but for the midrange designs I do I much prefer Vivado and its full integration (fpga is about 1/4 of my job). I took an Altera design for the first time since Max+II was appalled by its poor Modelsim integration (by poor I mean it didn't instantly work as it does in Vivado). I found myself manually edit
If you ran the same code at the same clock speed in all 3 fpgas, it would take the same time in every fpga. They are not processors - they allow you to design hardware. And hardware will always take a fixed time to process, depending on how you design it.
A short article on the design of the push-pull transformer: These are very problematic for newbies in power electronics, principally because in a classic topology there are 2 issues that dominate, namely; 1) leakage inductance &, 2) flux balance in the core - i.e. stair-casing of flux / Imag to failure. Many newb
I would say first do the analysis for ASIC impl. You will get a max clk value, above which you will have clock violations. Keep that fixed for ASIC. Use the same clk in your constraints file for fpga impl. If the fpga PnR tool reports violation, then reduce the clk to the required amount so that there are no violations and proceed with your work