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Hello, My goal is to find out how to synthesis and place&routing is affected after small modifications to an existing VHDL code. After a small change (e.g. halving the threshold frequency) in a bigger structure, I have to make sure that the not changed parts of the code post P&R should stay the same and be equivalent, so that I don't have to ve
Dea Forum Im designing a FIR filter, in this case a low pass. I get the coefficients from Matlab (no matter from where..) ,that are from 0 to 1, in floating point. Now, I want to implement this FIR in my fpga ,with buil in 18x18 multiplier. So,I transform the coefficient in integer value of max 17 bit (1 bit for sign) ,multipling the big
Hi, I am working with a project having around 70 DDR LVDS 910 Mbps connections to fpga. I am wondering if ZYNQ 7Z030 have enough LVDS IOs with at least 910 Mbps ? Another question, as there are two Ethernet Controllers in ZYNQ 7Z030, does this means that no Ethernet controller chip is required on the PCB and only Ethernet PHY port is needed
: 157251 157250 how do I plot the Phase margin and Gain of pll? i'm trying to do an ac simulation but got confused what to put at the inputs and what s
I can speak about the fpga tools, specifically Vivado. They don't have capabilities of an automatic wrapper creation. You must write the RTL for it.
Hello all, 157237 I am having a problem I can't seem to diagnose: I have a pll centered around a ~24 GHz VCO. The block diagram is shown above, defiantly not the best design, open to criticism. The VCO provides a N/16 output which is mixed with a 1.
This is second part of my post: I am a bit confused because this is soft-core with status stable and was checked earlier. Maybe reason of such many warnings is caused that it is old design (as far as I can see the project was made with Xilinx ISE10), The project also had some parts based on Xilinx Virtex fpga and is hardware dependend. See sc
Hi guys, I designed a pll, and I'm not getting to a locking state yet. I'm trying to debug the problem by observing the behavior of different signals. It seems that I'm getting only Up Pulses and the behavior is periodic. here is one that simulation that shows the periodic behavior of Up pulses: 157210 [ATT
Hi, can anyone recommend an EVN or stacked fpga system for capturing a still image? preferred 720p. I would like to trigger a snapshot - freeze the video and transfer the image via USB to a PC (via FTDI or Cypress USB chipset). The picture should only be transferred once the trigger occurred. This would be my first application with a camera
Hello guys, I have implemented a PFD and Charge Pump and I wanted to do a simulation for them as part of a pll. without the need to perform verilogA components in cadence, I understood there is a way to take a complete pll design in Simulink and replace some components with transistor level components from virtuoso. here is a link that de
Hello guys I am Will from Levetop semiconductor. Our main product is LCD/TFT graphic controller, support resolustion: 320*240 (QVGA) 800*600 SVGA , to 1280 *1024 SXGA. Support 8/16-bits MCU parallel interfaces, and SPI, I2C serial interfaces Built-in Ggeometric Drawing Engine: provide Point Drawing, Line Drawing, Curve Dr
I'm looking for old Altera EPM7128SL fpgas. On ebay there are many at a bargain price, but I don't trust them. Could you give me some advice on where to buy them?
hey I have a simple setup with P32MZ2048EFH144 It has no external oscillator. I have a simple code with Delay_ms(1000) which appears to work fine (the led blinks at about 1 second) But.... I think there is something I dont understand. Take a look: 156716 No matter what I set in "MCU Clock Frequency ", the blinki
Hello, i agree with @KlausST. If you are looking for theoretical information see links to these
Hello, I am looking for best way (in sense of speed and simplicity) how to connect STM32 MCU to fpga board (Artix-7). The comunication must be two-directional. I am experimenting with some kind of coprocessor for ARM CortexM4 core. The MCU is sending data to process for fpga and after fpga ended processing is receiving processed data. I (...)
Hi All, am appealing to anybody who has a similar environment to give me a few tips here :) The internet problem is weird, the system default is ffox 70 that runs fine standalone but none of the quartus menu's that would invoke it (help etc) work you just get no response. The same is true even if you set the browser path directly to ffox instead
Moreover your country could levy import taxes on electronic products (when the amount crosses a certain limit). So check that out. (If I buy an fpga board from Digilent USA and make it ship to Germany, I have to pay some euros extra as tax, which I don't need to pay if I buy the same board from Digilent German website).
I think we've had this discussion before but for the midrange designs I do I much prefer Vivado and its full integration (fpga is about 1/4 of my job). I took an Altera design for the first time since Max+II was appalled by its poor Modelsim integration (by poor I mean it didn't instantly work as it does in Vivado). I found myself manually edit
How is different compared to clock divider tutorial at ? One is using TSPC prescaler approach in CMOS gates ? The other is using counter approach in verilog ?
If you ran the same code at the same clock speed in all 3 fpgas, it would take the same time in every fpga. They are not processors - they allow you to design hardware. And hardware will always take a fixed time to process, depending on how you design it.