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21 Threads found on Fpga virtex4
Hi Where can I get example PCB projects for Xilinx fpgas? I found a project for virtex4 in the Altium example projets. But I want professional boards containing PCI Express, FMC connectors, Gigabit Ethernet and ...
Dear Miryama, Of course it depends on your design. How much bigger design are you using (including and fft)... The best way to know is to make one...U see as a proverb says, "when u do you understand" ...:) Then synthesize if you are using Altera or xilinx fpga, then Quartus and ISE will tell you how many resources have you used up. If excee
Hello friends, I have problems when analyzing vhdl files in the synopsys design compiler. I do not know why this is happen because I synthesized the same design in virtex4 fpga without a problem. Can anyone please point me out what cause the error below? signal cnt_req : std_logic_vector(1 downto 0); process(clk_i) begin if (
Hi, As we have developed virtex4 fpga Board, with PowerPC, So, please some body help me with porting embedded linux into the PPC. Thanks for the help in advance.
I'm doing image processing...i want to store my pixel values in BRAM...i have used rs 232 to take each pixel from PC to fpga.. i want to store each of these pixels into BRAM of virtex4 fpga if i'm using core generator is it necessary i have to use a .coe file?? can't i store pixels which are sent via an rs232 into bram?? how do i do (...)
Hello dollard, virtex4 is a chip, a fpga, and it does not have any display. Maybe your board named .... has a display attached to virtex4 you can use to display the word. Have a look to
Check this site:
HI ALL, How to do for SSTL2 Class II in order Interfacing Micron DDR Memories to Xilinx virtex4. Specific Guidelines for Virtex-4 fpga I/O Supported Standards UG070 Whe need resistor only for data bus and/or bus adress in not clear? thank's in advance best regards
You choose VCCO according to the requirements of whatever external devices you've connected to the fpga I/O pins. Here's a relevant section from chapter "SelectIO Resources" in the Virtex 4 User Guide UG070: Output Drive Source Voltage (VCCO) Pins Many of the low-voltage I/O standards supported by Virtex-4 devices require
Good evening My Board (written on the fpga board) is Board Vendor: Xilinx Board Name: Virtex 4 ML401 Board Revision: B Do you have any article or simple tutorial on microblaze microcontroller for virtex4 ML401? Please reply to me as soon as possible Thank you
Good evening, I have done the tutorial (EDK 9.2 MicroBlaze Tutorial in Virtex-4). I am using virtex4 ML401, not ML403. However , when I opened the Hyperterminal, the Hyperterminal does not display any output. My lecterer told me the problem might occur because when using the BSB the revision board is only '1'. But my board is is written 'B'. Is
I'm studying the operation of a new product ADC08D1500 Board, but how to download data from PC to the Board, into the part which is virtex4 fpga block? Is there any concrete operational procedures? Thanks
Hi I am using ISE 7.1i for virtex4 . MY Target fpga is on ARM926EJ-s Versatile Board. ARM9 is debugged using RVDS SW By USB Jtag connector on the board which communicate to the host PC through USB and translates USB command to JTAG Domain on my board. I am using Chipscope7.1i evaluation version for testing some signals. But Each time I get the
At this time, only the Virtex-4 FX has all those features. This page has links to info about all the features you mentioned:
hi does any one know the configurations of vrn and vrp pins of virtex4 fpga if the pins are configured as lvcmos33. thanks in advance
I am looking for examples or descriptions on how to interface a ddr-lvds a/d converter with a virtex4 fpga using vhdl.
partition your design.. well, regarding the data flow... However, I think that most important is the well-behaving fpga platform. - you can try board-level feedbacked DCM in virtex4(virtex5 is not available now except proto/es), PMCD etc. - And drop down the IO voltage. - reduce the IO numbers between fpgas (by using serial IOs?) (...)
Which fpga are you using? What parts of it are you now running at 1 Gb/s? Some fpgas have 10 Gb/s serial ports.
Check your fpga data sheet. Some fpgas provide configuration bitstream encryption. For example:
I programmed my xcf32p and it config my vlx60 successful. but when I make a encrypt .mcs file and download it to 32p, download the .nky to vlk60, push the reconfig button, but vlx60 do not work, it looks like not config probably, the fpga done pin did not go high. what's wrong? is there any special step to config encrypt .mcs and .nky? could you pl

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