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43 Threads found on edaboard.com: Freq Divider
Looks like a university homework exercise... Other than what is mentioned above, if you want to do it manually, you have to use various 200MHz freq divider logic. For that you need to write various counter logic in RTL.
If I have a clock of frequency F; I need a digital circuit that can generate frequency (M*F)/N; need Not be a programmable one for eg: given a clock of freq, a circuit to generate 2/3*F freq?
Why don't you arrange the divider ratio which is closest number of actual dividing ratio being as integer multiple of fundamental frequency?? It will give you an insight at least..
the statement signal max : integer := (100000000/(to_integer(signed(freq))*2))-1; bothers me. I think this only works with generics, not with a port input. So if you want Max to be kept up to date, you'll need to assign it differently. And why do you have an else clause with the clock? actually, he doesn't. "null"
I think the results u have are appropriate, Provided u r not looking for a wide band power divider. Ur designs results are for particular frequency.. 5GHz is ur center freq or band width ??
Hi all, I want to design a programable counter divider that divide N=8 to N=25 ,the freq of clock is 900mhz. Thank you for your help.
i basically divide the power of UWB antenna(1-12 GHZ band) in four parts Do you need each output with the full frequency bandwidth, or do you want to split the signal into 4 frequency bands?
Hi everyone, i need help to ensure the maximum gain and the stability of my boost converter. My boost operates with a freq of 100kHz and a inductor of 400uH. the out voltage is about 430v set by the divider at output. the peak of current in the inductor is 5amps and it is set by the sense resistor of a 0.2ohm. My application consists t
Hi! You can create enable ticks for registers in your design which appear with freq 2.5Hz. You need a counter that counts from 0 to 50M/2.5 = 20000000 - 1 = 19_999_999. In this example module data is written to reg with freq 2.5Hz: module mymod(clk, data, out); input clk; // 50MHz input data; output reg out; reg cnt
I designed branch line coupler for 1.6GHz. My desired frequency is 800-2500MHz. I want to design 3dB response for entire band width. How to design the broad band coupler for required band width.
Choose the faster one. Setup depends on frequency but hold don't. If setup/hold doesn't violate on fastest freq, it will not violate on slower.
Dear all, Could anyone give me a method to generate the 3GHz quadrature source? Since I need to use the quadrature LO signal to test my quadrature upmixer. I just find signal generator just generates baseband (low frequency) quadrature source. Thanks, wccheng
Hi, I would like to do waveguide power divider 3dB/3dB, but i do not know, how can I to do it wideband. I have rectangular waveguide R120 (WR75), freq. cca 10 GHz - 15.5 GHz. Can you help me? Thank!
It depends on your divider and multiplier values. You can set them according to input frequency .
Hello! I'm trying to build a simple frequency divider that involves a PIC and a quartz oscillator. It is not my domain so i kinda need some help in choosing and programming the pic. The ideea is that i should get a random frequency from the quartz oscillator (it is a didactic project so the division and the main freq doesnt (...)
Hi, as the divider has to cover very wide freq range(0-2G), I want to use true-single-phase structure to design the DFF. I am not quite familiar with this. It works well for 2G with 0.18um process. Can it support as low as several MHz or KHz? Thanks!
I think you need two processes in this design. process(clk) --divide this clock by some value so that the counter speed is properly set. end process; process(clk_divided) --a typical counter program clocked at clk_divided. end process; the idea for the freq divider in the first process can be done understood from the following link: [url=h
Hello, I have designed a frequency synthesizer to generate a Local oscillator at 428.925MHz. So far I have been unsuccessful generating 428.925MHz. As part of my testing I programmed the PLL to output the "R" divider output on the test pin. Everything was as expected, a pulse with a period corresponding to the comparison frequency. (...)
I am working on a monolithic CPW 4-way (maybe 8-way in the future) 2watts Wilkinson combiner with center freq 20GHz. BW is 4 GHz. The substrate is GaAs. The size is the major concern in this case. I want to use single-stage design to reduce the size. The problem is that the 4 or 8 quater-wave transmission lines have to be parallel with equal s
way to realize Synchronized clock 16 freq divider ,also the circuit can work above 900MHz, and the delay is very small. Simple way is 4 ffs! But this also is according to your clock architecture definition.