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Freq Sampling

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67 Threads found on edaboard.com: Freq Sampling
im confused with various of definition ? what is conversion rate ? is that conversion rate can be the sampling rate/freq? Or is that sampling rate is clk speed ? how if if a SAR ADC has clk speed of 24Mhz, requires 6 clk cycle to do in that case what will be the conversion rate ? How abt tis Ms/s & Mb/s ? is both same or differ
Can someone give me the part number an AD Converter having a sampling Rate of less than 0.5?seconds and input frequency > 20kHz... Please help...
The frequencys in discrete time lies in interval from 0 to 1 (or from 0 to 2pi depends on frequency normalisation). Therefore first you have to set sampling frequency Fs in continious time units (Hz). Then any "digital" f character frequency (bandpass or bandstop or any other frequency) of (...)
What 'll happen if the sampling freq is much larger than twice the maximum freq of the signal?
i am using the above sample and hold circuit for a 16-bit ADC> the switch is realised using both nmos(W=500n L=1.6u) and pmos(W=1u L=1.6u). the input voltage range is 0-2v. the sampling freq is sample pulse width is 100usec and hold period is 4.9msec. when in hold mode the voltage at the output first starts increasing and then starts de
Hi all! I've got a folded-cascode OTA with SC CMFB and wanted to look at its output noise. The clock sampling frequency is 64MHz, input signal bandwidth - 2MHz. I used PSS (beat freq 64MHz, 0 output harmonics) and PNOISE (1Hz-32MHz, maxsideband=30, no input noise source) for it. The results that I am getting are quite suprising: http
SFDR=Spurious Free Dynamic Range (i.e., the Dynamic Range also accounting for spurious signal) Fout=100MHz I believe indicates that the above figure is measured with a signal sampled at that freq. In eneral SFDR changes for different sampling speed. nathan