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67 Threads found on edaboard.com: **Freq Sampling**

Have you considered the scenario of lowering the 48 MHz **sampling** **freq**uency?
Let the FPGA input be 48MHz but use a PLL inside to obtain a lower **freq** which you might want to use as **sampling** **freq**uency.

PLD, SPLD, GAL, CPLD, FPGA Design :: 03-30-2017 08:35 :: dpaul :: Replies: **2** :: Views: **428**

You can plot magnitude characteristics easiliy by gnuplot.
Here x=omega/fsample=2*pi***freq**/fsample, fsample=**sampling** **freq**uency
j = {0.0, 1.0}
h0 = 0.021
h1 = 0.096
h2 = 0.146
h3 = 0.096
h4 = 0.021
set xrange
plot abs(h0+h1*exp(-j*x)+h2*exp(-2*j*x)+h3*exp(-3*j*x)+h4*exp(-4*j*x))
This FIR filter is simple Lowpass ty

Digital Signal Processing :: 05-11-2016 12:38 :: pancho_hideboo :: Replies: **13** :: Views: **1088**

hi all
i want to detect **freq**uency between 140k and 145k.for example when signal is 140k turn on led1 and when its 141k turn on led2

Digital Signal Processing :: 10-31-2015 08:52 :: hamid.abbaszadeh :: Replies: **6** :: Views: **1071**

Without knowing details of Matlab command, different **freq**uency results for different Fs would happen if your **sampling** **freq** was a sub-**freq**uency of the sampled one. I.e. when you do sub-**sampling** and the aliased component only is output.
Is your example case a real case or hypothetical ? I cannot work out (...)

Digital Signal Processing :: 08-02-2015 09:21 :: kripacharya :: Replies: **5** :: Views: **986**

Say I have a sensor that generates a signal of **freq** 30Hz and now when I sample this at 100Hz, which is above the 2fa;
The Nyquist criteria is satisfied. But the output of the sampler has lot of **freq**uencies right i.e., 30Hz, 100-30=70, 100+30=130, 200-30=170, 230....
Now if I dont do any digital domain low pass filtering on the output of ADC to

Analog Circuit Design :: 07-28-2015 06:31 :: ykishore :: Replies: **3** :: Views: **498**

Hi,
This probably a basic question about the relation between bandwidth and **sampling** time. I understood the following terms.
**sampling** time: Time between two consecutive samples while **sampling** a signal periodically
**sampling** **freq**uency: Reciprocal of **sampling** time
I am using a (...)

Electromagnetic Design and Simulation :: 07-03-2015 17:27 :: bilal_oct :: Replies: **6** :: Views: **2098**

Very surely, the problem hasn't to do with Nyquist theorem. But it's not clear what "**sampling** a low clock **freq**" exactly means for you. Can you show a timing diagram of the expected behaviour?
In the general case, we would assume that both clocks are unrelated and don't necessarily have an exact integer **freq**uency ratio, so the clock edges (...)

PLD, SPLD, GAL, CPLD, FPGA Design :: 05-04-2015 10:49 :: FvM :: Replies: **8** :: Views: **779**

hello every one , I m doning a project over ADC , in some intel report i read that for UWB receiver arhitecture atleast we want 528 MSPS 4 bit ADC for m-ary OFDM technique,inspite of the input **freq**uency being in range of GHz ,how does OFDM technique works for so less **sampling** **freq**.

Digital Signal Processing :: 05-18-2014 06:32 :: vivek kajla :: Replies: **1** :: Views: **763**

See the amplitude its 10^-13 which you can assume to zero.
Its negligible.
What do you mean by rerun.
- - - Updated - - -
Have a look at this This Script file Plots the Sine Wave with respect to time
%The red text are comment

Digital Signal Processing :: 11-06-2013 04:04 :: xpress_embedo :: Replies: **4** :: Views: **616**

Hai
We are using **freq**uency modulation since we are private FM radio station with **freq** 91.9MHZ
regards
Aneesh

Digital communication :: 07-04-2013 05:34 :: aneesholv :: Replies: **3** :: Views: **1015**

1. In order to resuce the time of polling all 256 signal lines
a) you increase the **sampling** **freq**uency to check high request on lines. ... if samp. **freq** > (present clk **freq**)* 256, then you can sample all signals in less than one clk cycle of your present clk. One more advantage of using higher clk for (...)

PLD, SPLD, GAL, CPLD, FPGA Design :: 06-01-2013 06:58 :: amitjagtap :: Replies: **5** :: Views: **2488**

Hello guys,
I have implemented an ideal ADC+DAC converter and I did an FFT analysis. I did a test with coherent **sampling** with rectangular window and everything was ok. Input **freq**. 1,376...MHz, 500mV, sinewave and a starting phase of -90?. That gave Me 7,96bits (8bits ideal).
Then I changed the phase to -60? and rectangular window and gave me

Analog Circuit Design :: 03-15-2013 00:41 :: AMSA84 :: Replies: **0** :: Views: **1487**

Hello,
I would like to start a new project, my idea is this: an acquisition system based on pic, maybe pic32 but not necessarily, **sampling** **freq**. 100kHz, 24 bit, streaming data to tcp/ip client. Number of channels: as much as possible compatible with bandwith.
Few years ago I made a pic32 based board that performs a playback of a wav file from a S

Microcontrollers :: 02-15-2013 08:52 :: el00 :: Replies: **0** :: Views: **674**

sir this is our program to display adc_ppm value on LCD using ATMEGA32 microcontroller we are facing problem in displaying converted value the result is in symbol form not in any value plz help me out as soon as possible
#include
#define F_CPU 8000000
#include
#define LCD_DATA PORTC // LCD data port
#define

Elementary Electronic Questions :: 02-02-2013 06:12 :: suraksha s :: Replies: **2** :: Views: **3724**

I have developed a simple costas loop for BPSK demodulation. It is working fine for 8Mbps data rate BPSK. The overall **sampling** **freq** is 125 MHZ. Inside the loop, the corresponding FIR and loop filters are running at 25 MHz. The lock range achieving is +100 KHz to -100 KHz of centre 30 Mhz.
Now, I am updated the same for QPSK demodulation. The up

PLD, SPLD, GAL, CPLD, FPGA Design :: 12-21-2012 07:37 :: demod :: Replies: **0** :: Views: **1285**

Hi,
if anybody know resamplin algorithm mean help me
**sampling** is used to take sample of analog varying quantity. like sine wave..
To get the approximated shape. Two times **sampling** is required then that of **freq** of wave to be sampled.
As the Nyqueist 3rd rule.
There are many **sampling** algorith

Digital communication :: 11-02-2012 10:38 :: kapilddit :: Replies: **1** :: Views: **755**

Hi
I found that the open loop gain of the SC CMFB opamp is **sampling** **freq**uency dependent, I use PSS+PAC analysis, it drops when **sampling** **freq**uency increases, same opamp configuration with SC-CMFB, the gain drops to 69dB at fs=5MHz. the DC gain is 75dB when fs=1MHz , with continuous time CMFB is 77dB.
any idea?
thanks

Analog Circuit Design :: 09-30-2012 23:50 :: prcken :: Replies: **3** :: Views: **734**

Hi,
I am trying to use the FFT library in mikroC to calculate the **freq**uency of input signal. The code gets complied but I am getting wrong and random results. The calculated **freq** does not match the input simulated sine wave. Following are the details of my code -
**sampling** **freq** = 1KHz
Signed Fractional Data Output from (...)

Digital Signal Processing :: 08-31-2012 11:03 :: karanbanthia :: Replies: **0** :: Views: **1931**

a single bit conversion is referred as TAD
if you have 8us for TAD you need at least 12 TADs per conversion so your complete conversion time is 96us which gives you 10.4kHz samplling **freq**...
it hardly gives you to convert a 5kHz signal....
by nyquist if you want to read a 60kHz signal you need MORE than 120khz as **sampling** **freq**uency.

Microcontrollers :: 05-08-2012 20:53 :: Kurenai_ryu :: Replies: **13** :: Views: **1475**

Given a TDM system with 4 channels, say 4 signals (bandlimited) to fm1, fm2, fm3, fm4 are muxed and transmitted, using a **sampling** duration of 1/fs (i.e., within each Ts, samples of all the 4 signals are transmitted).
What is the **sampling** rate for each signal?? Will it be fs*4???

Analog Circuit Design :: 10-13-2011 13:04 :: rsashwinkumar :: Replies: **1** :: Views: **879**

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