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# Fsm Design Question

13 Threads found on edaboard.com: Fsm Design Question

## FSM: Relation between number of States and Power

Sounds a wee bit like a homework question. Anyways, forget the fsm. Ask yourself: "what does power usage in general in an fpga design depend on?". You should know that at least. If you don't know, then go read a book / a Xilinx guide on the subject. And if you do know, then you can reason your way to the answer for the fsm (...)

## FSM: Moore or Mealy?

Hi, just a quick question... I have developed a fsm using VHDL and I'm questioning about if it is a Moore or a Mealy fsm. Here is the code: -- fsm states type state is (idle, init, init_shift, subtract, test, operation_sub1, operation_sub0, correction, finished); signal current_state, next_state : (...)

## Counter using FSM verilog

How to design a 8 bit counter using fsm based . .using verilog ?

## VHDL and VERILOG FSM encoding

Is it possible to control the encoding style (one-hot,gray,binary, etc...) of your fsm using your HDL code ?

## how to design a high performance paralell to serial module

Hi all my paralell output signal frequency is 48khz, its width is 24 bits. it has to be converted into serial signal. what my question is how to design a paralell to serial module with verilog. Maybe I can realize it with fsm or a sinple shift-register. which one is better. and the frequency of the serial signal is 48k*24 Hz? a

## modeling a sequential circuit for vending machine using moo

u are required to design a mealy type fsm dispense a piece of candy for 50 cent.The machine accepts 10 cent and 20 cent and coins takes 50 cent to dispense one candy from the machine.If 60 cent is deposited,the machine will not return the change but will credit the buyer with 10 cent and wait for the buyer to make a second purchase. enco

## VHDL question, what is the better architecture for this task

You have to implement the state machine inside the process block using the clock. You also have to use an enable signal to activate the fsm. On each clock edge (rising or falling) it will check the enable signal, and if it is asserted, then the fsm will execute upto end of the parallel to serial conversion. The enable should be HIGH when you have a

What are the different between fsm, ASM, Event driven circuit and clock driven circuit? thanks,

## about fsm partition and critical signal

Hi friends, I'v got two questions to ask. --1-- If the circuit need more than 10 commands to operate, and I wanna design a fsm to realize this function. The question is considering some other inputs, then fsm' s decoding combinational logic will be complicated slowing down the operating frequency? how (...)

## Suggestions for low cost ASIC synthesis tool

any synthesis tool will do exactly that , that is take RTL and convert it to gate level net list . But they are in simple verilog format. I don't know how large your design is , you did say it was 98% ananlog but the question is how big is digital not in % but gate count / area . If your fsm is not too big you could (...)

## Interesting Digital Design question

design a logic which mimics a infinite width register. It takes input serially 1 bit at a time. Output is asserted high when this register holds a value which is divisible by 5. For example: Input Sequence Value Output 1 1 1 0 0 10 2 0 1 101 5 1 0 1010 10 1 1 10101 21 0 (Use a fsm to create this) Any solution to this?????

## Change Mealy FSM to Moore FSM?

Hi all, I have read the book Verilog design Style Guide from The book said "you should use Moore fsm in principle". But my question is: can I change all the Mealy fsm to Moore fsm? What's the sacrefice to do this(e.g. add a lot of state)? And is there any fomular to do this work? BTW: Mea

## About the choice of FSM---Moore or Mealy

there are two good articles in snug from cimmings on fsm design. you can find them at