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How can we use INTEST,EXTEST and BYPASS modes without wrapper in DFT for design having IP to improve test coverage for ATPG. Is it affects any other things?
I designed a MSP antenna with patch dimensions of 15x17 mm for 2.4 GHz with return loss of -35 dB. (I can call it very low profile for 2.4 GHz). However, owing to shaping my ground plane, the antenna gain is quite low, -0.5 dBi. Does that antenna can be used with LNA for an application such as for cell phones, if yes, what do you think should be th
Hello, guys, how are you? First of all, I'm using Cadence and Layout GXL (IC version is 6.1.8). Process is GF_8HP (available via MOSIS). I would like to ask if anyone know how to solve the following issue: When generating a nfet_rf cell into Layout GXL, I get four erros in the "Annotation Browser". These four errors are short circuit error
Hello. How to highlight all differences in the layout as "flattened" and not as "hierarchical"? I'm using Calibre XOR + rve.
Hi, Please see the code below: module ha ( input a, b, output sum, cout); assign sum = a ^ b; assign cout = a & b; endmodule module my_design #(parameter N=4) ( input a, b, output sum, cout); generate for (i = 0; i < N; i = i + 1) begin
Dear friends, I found this cell from analog library of my foundry, it is classified as wide band amplifier, my question what the thing makes it wide band, what this architecture named so I can make further research on it Thank you Best Regards 158302
lithium ion batteries have a maximum discharge rate. this is a thought experiment. if i connect a 18650 lithium ion battery with a maximum discharge rate of 2.8 amps to an electromagnet, 1 wire is connected to the positive terminal and the other wire is connected to the negative terminal, without a resistor, would the 18650 lithium ion battery di
Can simulator like ncverilog simulates the metastability behavior of CDC circuits? How to do simulations with metastability models (RTL and gate-level)?
Hi, Suppose I have an incorrect nets error at the cell level in lvs. For eg: if I have a cell and2x2, and the tool is reporting "incorrect nets" error under this cell, besides the top level cell. My question is, since there are many occurrences of the above cell in the layout and source, on what (...)
Hello all, I have vcd file now I want to feed it to the analog environment or say cadence virtuoso environment.How do I do it. Thanks in advance
Hi all, I am fairly new to HFSS, and unlike python or MATLAB, the resources are few. I am trying to create a linear array such that I can simulate the beam pattern, get the array factor and also see the effect on the beampattern with and without mutual coupling. I havetrie the unit cell array method but I keep getting error when setting up the r
Hi, I'm I'm an absolute newbie in PrimeTime (PT) and would like to seek for help in the problem that i have here which depicted in the attached picture. notes: 1) net a & a_b and b & b_b are complemented pair. Example: a=1, a_b=0 and etc. 2) Control Block A and Control Block B have no dependency on each other. Any combination of net a and
Has anyone used these types of structures ?
I've been doing a lot of survey article for fanout for design compiler. But for some technology process such as 90nm/.18um , our target library (.db / .lib) has already the settings of max_fanout/ max_capcitance for our design, but in 4x nm process, I can't find the max_fanout in .lib file 1. Is that the reason for settings ?? (But how to determi
Hi , At the moment I am trying to perform parasitic extraction using PVS-Quantus to get the RLC parasitics of the metal stack (routing). the Pcell of my the transistor already includes RLC parasitics , I want this part of the layout to be blocked from parasitic extraction to avoid parasitics double counting To do that : ? I preserved the
I am trying to replicate a 4 X 4 butler matrix How should I emulate the MIMO encoder and decoder in Sonnet
Hi, I wanted to insert cell using script in innovus during eco. I intended to using ecoAddrepeater command for this, and wanted to add prefix for the cell added. (e.g. eco_fix_leak ) is there any way to add prefix to inst ? Really looking forward to your reply!
Hello all, I am wondering if any body has the issue with very long simulation time because of very large values for node voltages in trannoise simulations? in a few samples of monte carlo simulation of trannoise very large values happened in voltages in different bandwidth values.
Hi, Everyone. I have a complete design in Cadence Virtuoso, and I want to import a layout file of Cadence SOC Encounter to Cadence Virtuoso. Can I combine Cadence Encounter Layout and Cadence Virtuoso Layout together?
The picture shows resistive trim networks. I am using a 0.18um CMOS process. How should I choose the NMOS switch size (W/L) for the resistive network 1 and 2 ? What criteria decides the required ON resistance for the NMOS switches ?