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Hello All, I want to store the Excel File pointer in Flash Memory. I am using PIC18f46k80 in Mikro C pro. I want to just store two datas - Two pointer value 1st pointer for Write and 2nd Pointer for Read (I mean - From Excel i am reading after 1 Hour some data which ever written in 1 Hour) So, i need two pointer value after Power goes off a
Hello, I am using TSMC 180 to design a CMOS imager. I wonder if I need to manually add a passivation opening to let light to shine on my photodiode. Thanks a lot.
Hi again, I found below circuit on the youtube, I make it exactly like the schematic, it doesn't work and I check it many times I couldn't find any kind of problem so I removed inductor and cap for more reception but still it doesn't work:bang:, why?!!:cry: can you tell me where could the problem be? 150107 [URL="https:
Hi all, I see many EMF detectors on the Internet, they can detect EMF radiations below than 1MHz, Around 60 Hz calibrated, many of them, I found some of them with the wide band transistors so they can detect wider band of EMF like UHF band, but I can't imagine an IC version detect very wide band, like a KII EMF detector, so how KII can detect almos
I am trying to simulate a memristor crossbar array. But I found the sense margin is constant for 3x3 and 5x5. Theoretically, the sense margin should decrease with crossbar size. In the graph, the result that the 1st readout is higher than the 2nd readout is as predicted by the theory. I check the single device IV and it is the same like from th
Hi fellow engineers! I am doing a digital block for a mixed signal ASIC as part of my diploma thesis. I allready finished the digital design (with genus and innovus) and have it imported into virtuoso. Everything works fine up to the point where I have the post layout simulation of the finished asic with pads and simulate the design with 1nH induc
Hi all WHat does this mean in standard cell library? In here, what does 1000, 1001 mean? what is the unit? lu_table_template(delay_template_7x7) { variable_1 : input_net_transition; variable_2 : total_output_net_capacitance; index_1 ("1000, 1001, 1002, 1003, 1004, 1005, 1006"); index_2 ("1000, 1001, 1002, 1003, 1
We all know that .lib file is used in synopsys.I am designing a new standard cell and update .lib can anyone provide information regarding cell_rise and rise_transition and cell_fall and fall_transition and rise_power and fall_power . Regards K.Karthik
I am using siliconsmart to generate liberty files. I encountered an error in a cell with multi-bit pins. How do I set a parameter for individual bus pins? I want to set the partial swing of an individual bus pin to another bus pin. Thank you
Dear All, I am currently doing a project that requires me to use both CST and AutoCAD. Please refer to the screen shots below for the models that I have drawn in AutoCAD before exporting it to CST. The entire patch is solid which is not what I want. What I need is a gap in between the patch and the outer ring as shown in the picture below. I am una
Hi All, I want to compare power numbers of a synthesized design (based on umc65nm) with : a. the existing cell library XOR gate and b. A full custom made XOR targeted for low power (both meet x1 drive strength). I also have the back end data for the cell library, so that I can perform transistor level simulation for existing one. When I
Hi. I am using siliconsmart to generate liberty files. However, I am encountering an error in one of the cells. The tool cannot recognize the cell as clock-gating. Is there any option so as to solve this? Thanks a lot.
Hi, I was wondering if anyone knows how to convert the Synopsys (Milkyway?) tech file (file extension .tf) into an LEF file that I can use for Cadence SoC Encounter. The standard cell libraries that I am using have LEF files defined for them, but what I need is the technology LEF file. I have tried using "generateLef" command in Encounter, b
I am using siliconsmart to generate a liberty file. I am encountering an error during the import command. Error: Functional Recognition for the cell fusecellx8_v1_3v_5b is incomplete I checked everything (netlist, configure.tcl) and could not find the issue. Is there any way to know what causes the error?
Can someone explain me the format of a CDL netlist in detail. Does each and every subckt name in the cdl netlist represent a cell/macro reference name in the Block. If yes I am observing couple of subckt names (like .SUBCKT ICV_74) which are not found in my tile as cell/macro ref names. How do i understand to which part of my design do they bel
Hello Forum, I am working on the design of a Gilbert cell Mixer. My Goals are: 1. Vdd should be 1V 2. Total current Idd approximately equal to 500?A-1mA 3. Voltage Conversion gain >= 6dB I have achieved this with the circuit attached below. 149773 With inductive degeneration at the source of Gain stage, the
I am new to HFSS and am trying to model a frequency selective surface of tightly packed tripoles in an equilateral triangular (hexagonal) grid. I set up a trapezoidal unit cell with master/slave boundaries and floquet ports on each end and as long as the leg lengths are short enough to stay within the trapezoidal cell, there are no problems and the
Hi all, I'm implementing IP using Flip-Chip floorplan, so several IO ports must be connected to bumps. How to set attribute CLASS BUMP in LEF file for several IO ports when writing out LEF (not by hand)? Now this attribute is "CORE" by default. Tool - cadence Innovus 17.1.
I am working on my innovative idea that is GPS based Anti-theft module for devices. I am writing code in C. I need advises about how I can improve the module. It is either a stand alone module or it is embedded in the device microcontroller that is the code. It uses UART to communicate with GPS module and also user. When the device has to be fir
Hi. I am using siliconsmart to generate .lib file. For pin CK of one cell, I cannot generate a timing table. All the other pins have the timing except for pin CK. How can I solve this? Thank you.