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Hi, I am currently building a heterodyne laser interferometer in a Mach-Zehnder configuration. The output of my photodiodes give a phase (frequency) modulated signal with a carrier frequency of 80 MHz. The modulation signal has a maximal frequency of some KHz. Because I am completely new to electronics and signal processing, I have some fundame
I noticed that power gating cells are in the standard cell library (lvt). Can we use them in verilog level? If you know about how to use them, can you please share your experience or good references? Thanks
Hi, all. I have measured the power of a verilog module (simple booth multiplier) by using dynamic activities data and dc_compiler. With SAED90nm from TSMC, a reasonable power value is obtained. However, with SAED32nm, very small dynamic power is obtained. Especially, zero cell internal power does not look okay. cell Internal Power = 0.00
Hello Forum, I am working on the design of a Gilbert cell Mixer with reference to ( ) My Goals are: 1. Vdd should be 1V 2. Total current Idd approximately equal to 500uA-1mA 3. Voltage Conversion gain >= 6dB Width of all nmos = 3?m Width of all pmos = 8?m
I wrote a verilog code, then I synthesized it in Encounter RTL compiler and imported the design in Encounter, I was trying after that to import it to Virtuoso as a DEF or GDS, the problem is that I can only seen the metals and vias in both Encounter and Virtuoso but not the transistors. I followed the the steps in many tutorials and I'm still wasn'
Hi All, I want to perform place and route based on UMC 65nm node. However in the design kit, I cannot find above "physical only" cells and instead there are only filler cells (with/without n/p capacitors) and well tap cells. I was wondering whether the Endcaps and Decaps can be replaced by those filler cells with (...)
Hi, I am trying to compile the Open cell Nangate45 Library with the Synopsys Library Compiler. By searching how to do this I came across the instruction from . According to this it should basically work like this: 1. Starting Synopsys Library Compiler $ lc_shell[/COD
Hello All, I have been trying to learn more about the .lib syntax, and I am having trouble understanding pins with multiple internal_power groups. For example, OpenTimer has an example lib file which contains this cell (portions removed): cell (AND2X1) { ... pin(A) { direction : input; ... } pin(B) { direction
i have 6 cell 1865 from a dead laptop. the four cell have each 2.7 volts, and two have 2.2 volts.. is it possible that 2.7 volts can still be use? tnx
Do you want a burner-fired steam engine with a direct or belt-driven generator, or a direct-solar-concentrator / hot-working-fluid powered one ?? Proof of concept, or more than a few Watts ?? A few moments on Amazon found many options... But, given the eye-watering cost of the better miniature steam engines, unless you can locate a local steam e
Every country in the world should set up its own Government owned Design and Manufacture centre for designing/manufacturing electric car chargers for its own country?s citizens. This will prevent imports of huge amounts of dodgy electric car chargers by dodgy ?middle men?. Such dodgy chargers will result in disappointed customers, and tons and t
I am worried about the effect of frequency on dielectric constant and thus capacity of parralel plate CAPACITOR. C = KA/d C is capacity, K is dielectric constant of the medium between the two plates, A is area of the parallel plates and d is the spacing between them. Is this relation independent of frequency or this formula can be used at all
What can I use to replace transistor bf494 in a cell phone jammer circuit. Please i need your help urgently. 148785
Hello, I synthesized a design with Synopsys' Design Compiler and want get some statistics about the synthesized netlist. In particular I am interested in the number of stages/sequential cells from a flop-flop's output to the chip output. My idea was to get the path from the flip-flop to the output and counting the sequential cells in between, bu
how to implement a function of the following type sb(z) = logb(1 + bz) in a 2 - dimensional lookup table in verilog ?
Hi all, In Cadence Layout XL, the option place -> custom digital -> placement_planning, gives me the following error when I try to place the digital cells for auto place and route. Please help!! Error in virtuoso CIW: *WARNING* (VCP-3009): Could not run Placement Planning because the component type and cellType assignments in the design a
Hi all, In Cadence Layout XL, the option place -> custom digital -> placement_planning, gives me the following error when I try to place the digital cells for auto place and route. Please help!! Error in virtuoso CIW: *WARNING* (VCP-3009): Could not run Placement Planning because the component type and cellType assignments in the design a
hi i need to writ Arabic Letter on P10 Led Matrix 16*32 i have dmd library but can write only English this link any one have solution or another library support arabic
Hi, I have a hierarchical Calibre reuslts violation markers database, meaning it tells me in exactly which subcell each violation belongs to, and coordinate in that subcell context, and properties telling me the location of that subcell reference in the topcell. I want to take that DB, and remove the hierarchy, so that (...)
I am performing physical synthesis using DC-T of a design. I'm facing the following warnings/error: Error: No physical library cells for following library cells (PSYN-014) These cells belong to the ABC library. My design makes use of 3 std cells libraries. All of which contain different sets of standard (...)