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Dear Alturist, I have simulated and exported (S2P file) a microstrip reflector unit cell from Ansys HFSS. Now, I want to import this S2P file in Cadence virtuoso. Can anyone explain which steps should I need to follow to do this. From my knowledge, I know that analogLib contains two port components like n2port. This can be used for the s2p file
Hello everyone. Recently i simulated a structure using the CST microwave studio and took the s parameters from it, exported them as touchstone file and placed them inside a snp item in the schematic. This snp file has two ports only because my structure in cst had two ports only and i will work with S11,S21,S22 and S12 parameters. What i want to do
I am designing linear power amplifier for cell phone, all of our PAs (L/M/HB) need 2nd harmonic termination to get good linearity and PAE. Removing the 2nd harmonic termination degrades performance a lot no matter how we tune it. However I know that removing the harmonic termination while maintaining the performance is possible. Does anyone here kn
Hello group, This question is specific to tetramax tool. I need to know if there are tool commands or a TCL script or API in tetramax for the following: Trace the cells and nets from scan-cell clock pin to top PI/driving clock? extending further, I need to get the net paths for all the shift clocks of the scan chain elements traced back t
Hi, I have a design of a circuit that is synthezied using "lec25dscc25_TT" library. I want to resuse the design to synthesize it using Design Compiler, but I do not have this specific library. "lec25dscc25_TT". Could someone help, if I could get this library? Or is there any other way to synthesize the design, instead of writing the components li
Is any difference between the endcap cell and boundary cell (other than technology node)? why we placed the boundary cell at boundary of the core area of the chip?
156744 Hi, For a typical double balanced Gilbert cell, how to match the RF input to 100 ohm? The zero frequency input impedance should be infinity. Even when frequency increases, the input impedance doesn't change significantly at sub-6GHz range. I understand that inductive degeneration can help with input-match
Hi All, I have some doubt regarding timing arc. What is timing arcs. Is there any hardcore rule that if any port is asynchronous signal then it should have timing arc??
I'm looking for old Altera EPM7128SL FPGAs. On ebay there are many at a bargain price, but I don't trust them. Could you give me some advice on where to buy them?
The standard potential of a water electrolysis cell is 1.23V, applying a higher voltage doesn't increase the gas yield per ampere second but causes losses. Practical electrolysis processes operate at 70 - 80% energetic efficiency, the fuel value of the produced HHO gas is lower than the applied electrical energy. See
Hi, I am using PVDD1ANA as my I/O with TSMC 0.18um technology. When I try to pass any signal through the I/O, it is getting attenuated quite a lot. The I/O seems to be acting as a 2 Mohm resistor in shunt with the signal path. Does anyone know where I am going wrong?
i am using fuel gauge battery monitoring IC Bq34110. i have read state of charge battery calculate but not update dynamically. if power on/off then i will change ? and how to calculate EMF,C0,R0,T0,R1,TC,C1 for lead Acid battery for Bq34110?
I made a cell using copper and aluminum with liquid bleach electrolyte. I used two different meters to measure current. The analog meter highest setting is 250 ma and DMM has 10 amp setting. When using analog meter the current slowly climbs, but the highest I've seen is 200 ma. When I use DMM the current slowly climbs but may go as high as 3 amps.
Hi, What do the following warnings mean in Calibre ? - WARNING: cell <cell name> is referenced but not defined. Empty cell used - WARNING: cell <cell name> already exists, will overwrite Thanks, Aditya
For setting driving cells, theres a command -set_driving_cell $LIB $cellNAME But If i want to set a "load" or loading cell to all output ports, is there a similar function? If not, how do i set some cell (eg. buffer or level shifter) from some timing lib as the load to all output ports? Thanks
Hi. I am using siliconsmart to generate .lib file. For pin CK of one cell, I cannot generate a timing table. All the other pins have the timing except for pin CK. How can I solve this?
I'm using GPDK45 Layout is LVS clean Error logs : __________________________________________________________________________ *************************************************************** Reading schematic network Reading layout network inputting network test_1.ldb Preprocessing schematic network phase 1 Preprocessing layout n
Friends, Please review my custom voltage lithium-ion power bank and send me your valuable comments and suggestions. Below is the youtube link. Thanks.
Hi Guys, I'm learning about ASIC and am looking for some technology library. Someone share me some technology library (any library is fine). Thanks hungquoc
I am new here and don't know where else I might find an answer to this question-or which forum here would be best. This is a serious and important question so I hope it is not inappropriate here. As some of you may know, tens units or specialized devices are used by some for sexual stimulation. Some users will stim for hours at a time over the c