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1000 Threads found on edaboard.com: Fuel Cell
How to forbid a certain cell from being placed in cadence encounter?
1200 baud data transfer over audio passband of cellphone. Is that possible through the use of their codecs? Has anyone actually tried it? There are videos about comms on 300 baud but how about 1200 baud, has anyone ever tried it?
hi , can anyone guide me what we mean by saying a design is a 9 track design or a 12 track design? how do we identify our design in context with previous question? Regards .
hello, i would require some advice on the capacitive DC-DC Converter that can generate several selectable DC voltage sources from a single given DC voltage source. The generated DC output voltages are multiple times of the input DC level when unloaded. It uses the concept of the Dickson charge pump, by multiple flipping of the charged capacitor ont
Hi, Because of problem of Noise, I search for isolated converter device from UART to RS-422 based on optic and not with switching regulator. The communication data rate is 115200 bits/Sec. Anyone familiar with these devices ? Thanks.
Dear All, I would like to know if there any techniques for estimating the battery chemistry as well as its capacity in AH so that appropriate charging current can be decided. Thanks.
Hi, I have a question on physical design floor plan. what cells are placed around RAM? Why?
Hello, Has anyone used this NCSU kit for Analog Design ? Or is it mainly for digital design (standard cell flow). Thank you.
I have used Kavlico fuel pressure sensors for measuring fuel rail pressure in tuning EFI engines, but these I think go up to only 100PSI. Have seen ones for hydraulics that are rated higher (like 1000PSI) but have never had a call to use them. MAP sensors I have seen up to 3.5bar for turbo applications. None of these are digital, they put out
hi , in my current project , i am facing an error regarding site rows . it says site rows are overlapping. can anyone guide me how to resolve this error . Regards
Dear all, I'm facing a problem with a post-pnr simulation that I hope you can help me figure out. The design flow is based on the GPDK045 kit from Cadence. I use Genus & Innovus for synthesis & pnr, Modelsim for simulations, and I have compiled the standard cell library with modelsim for gate-level simulations. Post-synthesis, my timing co
I have a wall clock that uses 2 AA batteries. I would like to use a transformer, but I get frequent power outages. The clock uses about 30 mAh. It lasts about 2 months before it starts losing time. (Around 2.0 volts for the 2 batteries.) If I go with 2 D cell batteries, what kind of run time would be typical?
Hello, This posting is similar to an earlier posting: I do not have the hcells file. How do I create it or get it ? Can I use the Assura hcells file in Calibre setups ? What is it used for and what is the purpose of this cell file ?
Do we use .lib for gate level simulation of netlists?
Hi, I am trying to design BJT circuit using TSMC 180nm BCD gen 2 process. It is my first BJT circuit. so i'm worried whether the fabricated circuit will work well as simulated or not. TSMC gives unit cells of BJT. I will place a thousand of BJT unit cell to drive large currents. Is it works well as simulated? Please tell your experience abo
Hello all, I am unable to simulate D-flipflop properly in AMS. The input that i am giving is itself shown incorrect on the wave form window. I was able to simulate simple gates but find ing problems with D flip flop. Attaching the code and waveform. module DFF_VERI(D,clk,Q); input D; // Data input input clk; // clock input output reg
A Lithium iron Phosphate battery voltage is 3.2v and capacity is 5000mAh. what is the charging current if I make a charger for single cell ? Data sheet said that 1C rating. if 1C =5 amp for one hour that means a 5amp charger enough ? awaiting reply maxim
Hi, Is it possible to overwrite a cell delay after reading it from the liberty file by reading a new liberty file? in general, is it possible to read a second liberty file with different cell delays for the same standard cells? Thanks in advance.
Hello all! I'm pretty new to ASIC and liberty files and I was wondering if there was a general trend in liberty files and different threshold voltages. For example, say I'm operating on a library (I'll try to make it as general as possible so std cell, io or memory - any cell, any PVT) and the only variable that would be changing is the thres
Hi, I used the ddc file from DCT, and executed floorplan and placement. Timing slack after DCT is tolerable(0.6), while after placement is 8.2. Here are what i did. 1. created_fp_placement -effort high 2. place_opt -spg -optimize_dft -area_recovery -power 3. run" incremental opt" And here are my questions: (1) what else can I do to min