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1000 Threads found on edaboard.com: Fuel Cell
Hi, I am wondering if it is OK to solder directly the battery cell terminals for electric cycle. I am going to replace new cells in the battery. I have watched a video in which they do Spot Welding with Nickle Strips. Any suggestion which method is more reliable.
Searching legal location of lib cell "BUFFD1BWP240H11P57PDLVT" from (90.00300 227.28000), 4513629 attempts failed, current search location (0.57000 21.60000), current displacement 224.28224 um (934.50934 rows height) Warning: Could not find legal location for cell instance u_alb_srams/i_arccore_arccore0_bist_wrapper_top/arccore_bc_ram_0_inst/U1(BU
I am currently designing an antenna that exhibits a slight capacitative reactance (54 ohm -44j) Since I have crude prototyping tools (a VNA and nothing more than the toner transfer method to make boards at home), I was researching a way to test and replace SMD components on the matching PCB on the fly The matching network uses a differential ou
Hello, i have a problem to update the schematic of a cell regarding its layout by using synopsis. In cadence, i know how, but unfortunately not in synopsis. There is a button for autom. Update for the layout regarding the schematic, but without any other options. I would be thankful for your help.
Hello, I use a 3.7V 16850 cell that gets boosted to 9V (board : ) as I sometime, have to recharge my cell, I thought I'd use 3.3V coming out of a LM3940 but the booster output drops to 4.4V while the output voltage of the LM3940 drops from 4.0V to 2.2V I
Could anyone help to derive D flip-flop mosfet-level schematics from the following CMOS layout described in this conference document : Open cell Library in 15nm FreePDK Technology ? 154258
Dear all, I am new to innovus tool. I have attached the timing report taken after placing my standard cell. I would like to understand a few things in the report. What does TNS = 0 mean? What does max_tran mean? It is giving a negative number. What does that mean? TIA
Is it because of convention or because wires would be longer ?
Hi everyone, hope this topic has not been solved already (I don't think so). Apologies in advance for this long post, but taking time explaining things may help to explain my issue. I am currently working on the simulation of FSS transmission characteristics with the frequency domain solver of CST Microwave Studio. From theory:[/U
How does the two inverter delay stage in Figure 6.14 on page 265 of Design of CMOS RF Integrated Circuits and Systems helps to eliminate dead zone in Phase Frequency Detector
Hello, In the timing libs, I can find the "output" ports, see their "Related_pin", and report delay calculation from related_pin to output_port. However, how can I do this for all output ports and their related pins automatically? Basically I receive a timing lib from a designer that I know nothing about (Except the lib itself) of a single cell
I am trying to replicate the microstrip low-pass filter in SonnetLite from the book by Jia-Sheng Hong - Microstrip Filters for RF Microwave Applications, 2nd Edition (Wiley Series in Microwave and Optical Engineering) (2011, Wiley) However, the S12 graph sho
hello, can you please help with this error in ADS, the error is related to using Modelithics, at one point i was able to change the MODELITHICS_FILE value and then it worked for Murata Modelithics, now, i am having issues with KOA or Koyecera resistors Modelithics as shown below Cannot use defaults design "mmWave3_mm_lib:defaults:schema
Dear friends, When I do layout I usually connect the gate of the single matched array by extending the poly. it is easy to implement and I think that extending poly might be better than pitting via per every gate to move to metal connection as the via also introduce resistance, however in the book of the Art of layout design he suggested to
Hi, I'm hoping someone can help. Im looking to get 1 led on at nightime only. But it can only be 15mm deep. Battery as well. Its for a wooden fridge magnet. Is it possible to do? First Post. Be gentle.
Hi everyone, I have three types signal: Long string signal (several us), Low Frequency Periodic Signal (30MHz) and Supper Speed signal ( 10Gps). The maximum clock I can use is 30MHz. How can I detect the long string signal with minimum delay? This image show detail the signal. Thanks, 153588
We are testing a fabricated chip with expected output current of around 4mA which is then used to charge a button cell. The input is from a PV cell. However, when we attach an oscilloscope probe onto one of the pin outs of the chip (i.e. the ring oscillator and the clock), we detect a significant current drop at the output, from 4mA to around 1mA.
I am tying to charge a 4.7mF capacitor from a boost coverter, which is limited by very high resistance (100ohm) of its power supply. Anothe words, due to this the capacitor will be charged very slowly. 153405 What happened is when the C1 voltage reaches Vmax after soft-start (charging via R3 initially), the capacitor
Anyone have Tatsuno dispenser RS485 protocol/ manual. kindly send me at
Hi, Can I know the ASIC gate count of Spartan-6, Artix-7, Kintex-7 and Kintex ultrascale+. Or else I want to know how to calculate ASIC gate count using their respective logic cells.