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1000 Threads found on edaboard.com: Fuel Cell
Just wondering what this "frosting" on the Ni-Cd battery cap could be? How is it created? Is it dangerous? Should it be removed? Check the pic below.153287
Hi, Battery cell can deliver current based on load. I'm using Samsung 33G cell, which has 6A continous and 9.75A discontinous discharge current. Can i use it for 9A for 20mins ?
Dear friends, In my layout design I can change the aspect ratio (W/L) for the unit cell transistor in the matched MOS array. I can decrease it by increasing the array order or by increasing the number of fingers in the transistors. My first question, 1. why I always see people talking about reducing the aspect ratio to make it square for
I am assuming some button cell like a cr2032 has died. But it's no where mentioned in the user manual. Am I on the right track? Should I open it up looking for a button cell someplace? It's not holding date/time and all the settings are messed up on a power-on even after a few minutes.
Dear Colleagues, I am trying to import a CDL netlist into IC.5.10.41.500.6.147 and having problems with 3-terminal capacitors. The error message I am getting is as follows: ##################################### Capacitor Instance: c380 ##################################### ...Searching for a valid mapping in the dev-map file... ...B
Hi! Today I encoutered a problem when porting a digital block design from innovus to virtuoso: I extracted the netlist from Innovus with save netlist aswell as the DEF and imported them to virtuoso. During LVS in virtuoso I discovered that all of the Flip-Flops with reset (the synthesis tool seems to take them in around 10% of the cases a FF
Hello I am considering using the topology shown in "A Compact Power-Efficient 3 V CMOS Rail-to-Rail Input/Output Operational Amplifier for VLSI cell Libraries" for implementing a class AB output stage. It is stated several places that this topology is suited only for moderately low voltages as the supply voltage is limited by two diode volta
Diagnostics are meant to diagnose what is the status of the operational aspects of the car - specifically the engine. Whether it is working OK, or whether there are some parameter values which need attention for proper working. I do not see how the odometer OR the current fuel tank reading could have any bearing on a diagnostic. Th
We can evaluate frequency characteristics of z-domain transfer function, H(z) by using Verilog-A in Cadence Spectre. Assume H(z) = (1-z^-1)^3 = 1 -3*z^-1 +3*z^-2 -1*z^-3 Here we have three options as expression in Verilog-A. (1) zi_nd(V(Input), {1, -3, 3, -1}, {1}, Tsample); (2) zi_zp(V(Input), {1,0, 1,0, 1,0}, {0,0}, Tsample); (3) zi_zd(V
We have requirement for the single cell 3.7V Li-ion/Li-Po battery charger with inbuilt over charge and discharge protection. And we also need the Buck and boost converter for the regulated output voltage ( 3.3V and 4V) at the output end. The input charger supply is 5V micro USB. This regulated power supply will be used for ESP32 nodemcu and GSM
Hi Team I am using TSMC 65nm 0V-1.2V technology to tape out an IC. I created a filler cell with substrate contact as this. 1. Create a unit filler cell with a unit layout connect M1,3,5,7 to gnd and M2,4,6 to vdd 2. Add substrate contact form M1 to gnd.(I heard there is no such thing as too much substrate contact) 3. Fill the opening
Dear friends, I would like to ask for your help if you can support me please with some tutorial about Model Generator tool in cadence for creating matched layout cell. I tried to find some videos or tutorial in internet but couldn't find. I already read the help from cadence but unfortunately not able to get his explanation in practical. F
I'm aware that the Foundry provides the different models - ss, ff, tt etc - which will be used to characterize a standard cell library and extract the .libs. And we use OCV's, which basically say that a single type of cell can vary across a die which in-turn causes variation in its delay. I'm curious to know HOW does the foundry analyze these mo
From Sedra & Smith, there is an NMOS differential pair in Fig.1, with a resistor Rs connected between the sources. 1. What's the effect of this resistor Rs? I think its small signal, differential "half circuit" should be Fig.2. So its effects should be improving linearity by reducing Vgs, higher bandwidth, at the price of lower differential g
Hi dears I study numerical electromagnetics , especially FDTD method , i reached to the point at where i introduce my sources then i get an understanding problem .. at this method ( as in the attached photo ) the electric field is defined at time (t) and magnetic field at (t+dt/2) and there is a space separation between them equals half of the c
Hi All, If I have a one cell Li-ion battery and it goes to a boost conveter with transient loads at the boost's output. I want to minimize the droop at V_batt. Can I place several bulk caps (such as 220uF, 470uF, ect) in parallel with the battery when the boost has its transient at the output? If the battery is a normal DC power source,
Hi All. I am doing a project which is a Li-Po (Single cell, 6000mA) Powered ARM CPU based device. It have USB-C receptacle and SD Card. The CPU have USB 2.0 and USB 3.0 both in OTG. This device mainly feature: -# File transfer between PC (USB 2.0 or 3.0) and Board's SD card (USB Device Mode) -# File transfer between SD card (USB 2.0 or 3.0)
Hi team, I am using TSMC 65nm and trying to clear metal density errors with auto dummy fill. I have a file called "Dummy_OD_PO_Metal_Calibre_65nm.22b", which TSMC says this is the Calibre dummy insertion tool. I opened the file and changed the parameter of layout path as the directory to my library and layout primary as cell name LAYOUT SYSTEM
whenever I try to add BAT54 SOT23 diode in ads layout it shows a dialogue which says: The cell " " does not have the same units and database resolution as the current design. What should I do?
Hi team, I am using TSMC 65nm and trying to clear metal density errors with auto dummy fill. I have a file called "Dummy_OD_PO_Metal_Calibre_65nm.22b", which TSMC says this is the Calibre dummy insertion tool. I opened the file and changed the parameter of layout path as the directory to my library and layout primary as cell name LAYOUT SYSTEM


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