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Let's say we have a flop declared like this. When we = 0, it is assumed that ram will hold its value, and when we = 1, the value will update to din. If we don't specify what happens with else, why does this construct implicitly loop the flop output into the input of the mux even though we haven't told it to? always @ (posedge clk) begin
So, I am trying to simulate QDSC using Silvaco Atlas, the models I use for the solar cell simulation are (conmob fldmob consrh fermi optr auger bgn), the simulation runs fine with only the solar cell. But when I define the Schrodinger-Poisson Solver's mesh and define the region for QD then apply the Quantum models, which are (electron quantum new.s
Hello, I was trying to rerun the same verilogA code again, but I face this error: Internal error found in spectre during AHDL read-in, during circuit read-in, during hierarchy flattening,. Encountered a critical error during simulation. Submit a Service Request via Cadence Online Support, including the netlist, the Spectre log file,
Hi Guys I am designing a filler cell for my mixed signal circuit. I design is with 2 principles: 1. There is no such thing as too many substrate contact 2. I want to add sufficient bypass caps So, this is my single filler cell152777 In the center is a dc bypass cap and surrounded by a guard ring from substrate conta
Hi Team, I am using TSMC 65nm CMOS technology to layout a mixed signal circuit. I am finishing up my layout with a few questions 1. I am planning to use the CUP(circuit under pad) pad with 60um pitch distance as my I/O pad. And I want to connect the pad to an ADC through wire-bonding and PCB. This is my first tape-out and I am worried my output
Dear friends, in the next week I am going to start with my layout design. I have big fully differential amplifier circuit. I remember from my past work the problem when I finish with my layout and running the layout versus schematic then if I have an error it will be hard to identify and or more difficult to correct it. The difficulty will rise
Hi. Do the emissions of cell phones latch-up some integrated circuits, alter their operation ? When are emissions stronger; during ringing, placing a call, talking, reporting to tower ? Example : Remote controls ceasing to work properly if share a night table/shelf with a cell phone. Can the pre-programmed codes be altered when exposed to
Hello, I would like to ask: How to generate differential (two lines) clock from "normal" clock (one line). The clock frequency is 100 MHz. Project is written in Verilog and I am using "ISE Webpack 14.7" (Windows10 Pro) for synthessis. My FPGA is Spartan6 (XC6SLX9 in CSG324 package) on Mimas V.2 board (Numato). Thanks in advance and Regards
Hello all ; How can i chose the value of the resistor (Rs and Rsh) to simulate a PV cell (electrical circuit model)? Regards ,
Hi, I've been trying to do a layout on the NCSU Design kit provided technology (AMI0.6u). I am testing a layout on a simple inverter. Everything works great initially, I was able to do DRC, Extracted, and LVS and pass. However, it suddenly won't work today once I want to do a LVS again without me doing any modification. The error me
Hi all, In three stage ring VCO, we feed the current by single current source to all inverter/delay cell. Can we feed each inverter/dela stage with separate current source? What will be theh effect? Thanks in advance.
Hi everybody! I'm trying to simulate differential impedance of a couple of microstrip lines in ADS. I've found this post: Where volker@muehlhaus and tony_lth provides a really useful workspace to achieve this, but I'm not able to get it simulated
Hello to everyone. This is my first time on this forum and my first post so please go easy on me :-o I'm a software engineer currently working on a project for a gas station, and need to program TOKHEIM DIA-DIS or DIA-ITM board. I really need just a simple program to notify when the nozzle is lifted from it's natural p
I want to control a simple relay from both my cell phone and my desktop computer. This will be a simple, one command system: I give the command from either of those devices and a relay opens for about 30 to 45 seconds then automatically closes again. This only needs to be operated from within my house, but if I could do it from remote locations, th
Hi all , In book Verilog-AMS he is providing an example of a listing that can use another previously developed module by using statement ' include "moduleName.vams" I tried to use this in cadence virtuoso by copying the previous module in the same cell or even in the discpline.vams directory but still he could find my previously developed module
Hello How to write software for robot that can move all over moon surface and send images video of moon and after that i can go to moon and drink water make house and rest on moon and come back to earth and watch internet on moon and make cell phone tower on moon kitchen on moon and dry my cloth on moon and study on moon
Hello, As the title, do you have any idea for the problem: "Given a netlist, write a code/pseudo code for finding all the logical drivers of a pin of any standard cell in the netlist". It's easy to get all the logical drivers from design by tcl in tool. But in netlist, I have no idea. :bang::bang: Thanks
Hi people, I am currently interested on cell characterization methodologies and looking for ".lib" file creation. I have a little confusion on three state cells. Let's consider a three-stete buffer cell, I see on several ".lib" files rise and fall transition time w.r.t enable pin. Rise/fall delay/transitions w.r.t to data pin when (...)
Hello, As the title, do you have any idea for the problem: "Given a netlist, write a code/pseudo code for finding all the logical drivers of a pin of any standard cell in the netlist". It's easy to get all the logical drivers from design by tcl in tool. But in netlist, I have no idea. :bang::bang: Thanks,
In this paper 15.1 mW 60 GHz up-conversion mixer with 4.5 dB gain and 57.5 dB LO-RF isolation , I have three questions : 1) Have anyone designed a balun in spice software