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1000 Threads found on edaboard.com: Fuel Cell
Hi Guys I am using TSMC 65 nm PDK and I am working on I/O design. It came to my attention that I need to place a cell called power on control (POC), "to avoid the I/O unknown state during power-up. An unknown state might result in I/O crowbar current or bus contention when the I/O voltage is up before the core voltage." To the best of my understan
Does somebody know what is structure of metamaterial unit cell used in Metawave's radar provided on the image below? Is it metamaterial radiating element + varactor diode, or it is metamaterial phase shifting layer with some patch radiators underneath? references:
try asap.asu.edu. Arm also provides a standard cell library and a design methodology for this academic 7nm PDK. See:
Hi everyone. I'm still a beginner and I'm preparing a program that displays the current weight on node red using a load cell and hx711 and raspberry pi3. I have the python program that calculates the weight it works well but when I try to associate this with node red I'm completely blocked since I would like to take the result generated by my pytho
do clock cells on the clock path add to jitter? For every clock cell we add on the clock path, we are adding random latency through it. And different clocks on different clock path could have very different jitter? 1. won't this make the jitter on the clock much worse? 2. does this also add uncertainty to the skew?
Hello All, Iam trying to find out P1d, IIP3 for Gilbert cell mixer circuit.Please reply me how to find them in Hspice rf using Cscope. Please do help me.
Hi Guys, I am thinking how to better realize disabling power of circuit in undervoltage situations. Many DCDC converters have UVLO at about 2.8V that could be suitable for 1 cell battery, but I am designing 12V battery powered circuit. Some DCDC also have adjustable UVLO, but because I need to use large resistors for UVLO voltage divider so th
Hello all, How can i chose the value of the resistor (Rs and Rsh) to simulate a PV cell (electrical circuit model)? Regards
i got a warning message at synthesis stage saying "Library cell has no output pins defined. : Library cell 'BOUNDARY_LEFTBWP40P140' must have an output pin." and some other cells with same warning. these cells are physical cells defined in library.can i ignore this warning or do i need to fix it? (...)
Hi Forum, I ran a synthesis using design compiler for a using standard cell library which has operating conditions(Voltage=1.05V, Temp=25C). Now I want to run synthesis for different operating conditions (voltage=1.05V, temp=25C). I used DC command set_operating_conditions to set the operating conditions which I want and ran the synthesis. I am
Just curious, I have Calibre tool for check almost everything of physical verification. But I still need more extraction check from diva tool. For the one who does not know. We can extract a signal from layout with diva rule. For example I would like to check all METAL and VIA layer of VSS signal. I will write a diva rule and put it in Verify -
Hi everyone. I am looking for a book or a paper that gives a design procedure for mixers in general and CMOS Gilbert cell in particular. I have Razavi's and Lee's books but they don't explain the design steps for Gilbert cell. I would really appreciate any help. Thank you very much Abdulrahman
I am trying to run a HSPICE simulation which involves testing for process variation and effect of noise on the circuit. The HSPICE models that model the process variation require me to run a Monte Carlo simulation. Moreover, the models are encrypted so I cannot modify the parameters or even know what is being modified. I have to use a transient
1. What is the main purpose of a mobile phone? The earliest smartphones let users access email, and use the phone as a fax machine, pager, and address book. In recent years, the purpose of the cell phone has shifted from a verbal communication tool to a multimedia tool, often adopting the name ?mobile device? rather than being called a phone at al
1. What is the main purpose of a mobile phone? The earliest smartphones let users access email, and use the phone as a fax machine, pager, and address book. In recent years, the purpose of the cell phone has shifted from a verbal communication tool to a multimedia tool, often adopting the name ?mobile device? rather than being called a phone at al
Greetings, I want to know what is an optical interconnect in terms of the memory technologies. Also, if anybody could help me with these terms in computer architecture- Optical RAM cell and Optical Cache memory. Thanking you in advance.
Tools and Tech: ST 65nm | LIBERATE Library Characterization Platform (x86_64) 12.1.4 (altos 121) | Cadence Virtuoso 6.1.5-64b | Calibre Interactive - PEX v2012.4_16.11 I am trying to characterize a full custom designed cell. Parasitics are extracted using Calibre Interactive - PEX v2012.4_16.11. The extracted netlist is CE
In the area report for Leonardo Spectrum it is giving number of gates under the label of area. But the area of an ASIC design is different from the number of gates. Then how are we supposed to calculate the area and the Gate Equivalents when only the number of gates is given? 151234
In a Brokaw cell during startup, how high does vbg need to be pulled up by the startup mechanism to snap out of the undesired operating point? I have heard it may be more than a VBE.
TOOLs and Tech: Questasim 10.5c-2 / Synopsys design_vision I-2013.12 / STM 65nm Hi I am running some timing simulations on my design and have some doubts and issues with the results. 1- My design is synthesized with Clk_Period = 2 ns and the timing report of the design shows it could meet the timing completely (slack (MET) = +1.75). To me i