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Hello all, I am new to this forum and I have found it a very exciting and resourceful place. A little background. I am an electrical engineer and I live and work in Nigeria. We have frequent outages in my country and sometimes it takes weeks before the utilities even know the status of a transformer. This results in people being in darkness f
Hi all, I was hoping somebody can tell me why the below rf detector is not picking up any cellular phone signals? I am using through hole components and have soldered everything onto a CNC made PCB boards, keeping all tracks as short as possible (see image). I have no problem detecting 27Mhz, 40Mhz (wireless home phone), 466Mhz (walkie-talkie) b
Hi, I'm learning DFT and trying to finish my design with DFT compiler. After I run command "dft_drc" in DesignCompiler, I found thousands of warnings on clock as "Clock input CP of DFF xxx was not controlled. (D1-1)". I tried to debug this with design vision to find that the clock input CP is marked as "x", which I think should be a toggle clock.
Tools: Synopsys design_vision 2013 / Questasim 10.0d / tech ST65nm I have several issues with simulation of my synthesized netlists from design_vision. 1- As a simple design, I synthesized a generic multiplier. Behavioral simulations go well, simulation synthesized netlist, the simulator generates several intermediate values which I cannot fig
Have you ever done timing simulation with ARM standard cell library, especially full adder ? There are 3 inputs (A,B,CI), 2 outputs (CO,S) for the full adder and it looks like missing specify statements for them. When CI == 0, A == 1, B == 1, the outputs should be CO = 1, S = 0. And when A,B fall, CO also falls to 0. If there is some delay bet
Suppose I have designed two different unit cell of different structures for different frequencies, if I combine this structure to form a double layer structure (without disturbing the original dimensions). Will it disturb the original resonance frequency?
what tests should a standard cell qualify to be called as a robust standard cell ?
Can someone help me iin identifying where I can check the x snap spacing and y snap spacing of silterra 130nm? I cant fnd in any document. Does anyone know the X snap and ysnap spacing of silterra 130nm for layout?
Hi, I have not quite fully understood about the harm due to the ionizing affect of alpha particles in medical physics. Upon preliminary Google search, I found an article briefly summaries the affect as follow: 1. cell dies 2. cell repairs itself 3. the cell mutates incorrectly and can become cancerous. However, the (...)
I want to simulate the J inverter in ADS...How can I do? I want to get like this plot 150622
Dear when i do layout using tsmc13rf i created via (M1-substrate)&(M1-nwell) so when i using tsmc65N i am missing via (M1-substrate)&(M1-nwell) bulk .kindly your advice
Can somebody share what are the best techniques in FPGA design that can be used to estimate the logic cell utilisation in an FPGA even before the RTL is written in (VHDL or verilog) so that FPGA selection can be done accordingly to avoid last minute surprises. Thanks
Hi guys! I am working on a digital part of a mixed signal design. I am using LFoundry 150nm technology. When I synthesize my design with a fclock of 1Ghz with the typical library I can meet the timing, but when using the wort lib (not even the worst150degree, the worst just uses a reduced VDD) i get a WNS of -300ps. I am still a beginner in ASI
I attached the circuit here, it use op amp negative feedback to control the charging current of the 3.8V battery by regulating current of R1. 150387 And simulation result here 150389 it seems that the opamp + and - terminal are not equal to each other, thus the circuit is not working, I wo
What is the impact of using ram vs flops for a fifo? I know ram can be smaller and so uses less power. What is the downside of using ram here?
I am having trouble in defining in a unit cell of loaded three legs frequency selective surface in CST. Can anybody give me a hint. thnk guys
i am trying to interface cst and matlab. i am trying to run frequency domain solver with unit cell boundary conditions and i want to define port in the solver at Zmax. kindly if any anyone tell me the invoking code.
i am trying to interface cst and matlab. i want to invoke a plane wave as a source for the unit cell. please any one tell me the matlab code for invoking plane wave by matlab in cst.
When I check LVS of a CHIP level layout with hcell, there is some sub-cell (which is defined in hcell file) is incorrect. But when I check it manually (single cell check), the LVS result is correct. Could you please let me know what is different between hcell check and single cell check. (...)
In order to prevent atenna effect, there are 4 methods which I know. 1. Metal jumper 2. Poly gate area modification 3. Add diode cell protection. (N+/PW for NMOS; P+/NW for PMOS) 4. Add well ring to create junction like diode protection. (Nwell ring for NMOS, Pwell ring for PMOS) In the method 3, 4, could you tell me what is different betw