278 Threads found on edaboard.com: Function Verilog
I am trying to do function verification using System verilog. I have DUT developed in verilog. The DUT is very complex.
I would like to run multiple test on this DUT, from batch mode. The compilation and elaboration of the DUT takes long time in the whole simulation process.
So I am wondering is there a way I can compile, (...)
ASIC Design Methodologies and Tools (Digital) :: 03-27-2017 09:35 :: aarthy_maya :: Replies: 3 :: Views: 684
I would like to generate a step function which will generate a stair signal. The code is following:
if (count <=(stps-1) ) begin
@(timer(period, period, time_tol)) begin
x = x + (0.6/(stps-1));
count = count+1;
end else begin
x = x;
But there are some sharp transitions which are creating convergence error,
Analog Circuit Design :: 03-17-2017 13:36 :: ashrafsazid :: Replies: 6 :: Views: 873
input clok, rst;
sipo str1 (.din(data),.clk(clok),.dout(out),.reset(rst));
convol_enco u3 (.coded(coded_out),.in(data),.p_out(out));
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-01-2017 16:46 :: ecasha :: Replies: 2 :: Views: 575
Still there exist many bugs in Z-domain function of verilog-A.
So I don't recommend use Z-domain function of verilog-A.
Analog Circuit Design :: 02-10-2017 09:10 :: pancho_hideboo :: Replies: 7 :: Views: 1378
pls help me i need verilog code for biphasic waveform generation
This forum doesn't function in the way you think.
Tell us about the design scenario. Describe the problems you are facing. What part of a the code you don't understand. Show us what you done!
Members will help you in these aspects.
ASIC Design Methodologies and Tools (Digital) :: 12-16-2016 08:19 :: dpaul :: Replies: 9 :: Views: 1121
can any one help me how to implementation this function verilog modelsim VHDL
W C N 4 bit
N is radian
verilog modelsim VHDL whats that mean?
if you are using verilog, re you able to use any ip cores or you need to design your self??
what is the format of the 'N', i mean h
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-05-2016 04:43 :: dipin :: Replies: 3 :: Views: 557
I am prejudiced against using task (the only reason is because I have myself never used it and most legacy codes/cores do not use it). I remember using function once and it was synthesizable.
In my opinion a clock is necessary. Since there is no clock, your use of blocking statements is justified
But you can use tasks inside a clocked always
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-25-2016 09:15 :: dpaul :: Replies: 15 :: Views: 1087
this does 3/2=1.5 instead of 3.3/2=1.65
and for 3.7: 4/2=2 instead of 3.7/2=1.85
Is this happening with the value displayed or the value effectively stored at the variable ? In other words, assuming that you're using the $Display function, are you using the correct formatter ?
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-11-2016 14:09 :: andre_teprom :: Replies: 12 :: Views: 1001
You can use verilog-a for implementing this function.
Analog Circuit Design :: 11-07-2016 04:40 :: deba_fire :: Replies: 2 :: Views: 573
Is this possible placing the if statement inside the genvar and for look because I want to check each element of an array zero or not ? And then assign specific function for the values if its zero or non-zero element? Because when I tried the above syntax its throwing an error "A is not a constant" ? Thanks
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-04-2016 17:34 :: ads-ee :: Replies: 8 :: Views: 1033
In my experience, many company use below approach to design hardware by verilog/VHDL:
1/ Understand the requirement or the function of design.
2/ Describe the design in schematic or block diagram. It is not mandatory but it is better to make it closed to gate level ( AND, OR, NOT.. FF, RAM .) with connection.
3/ Write the
PLD, SPLD, GAL, CPLD, FPGA Design :: 08-03-2016 05:49 :: TrickyDicky :: Replies: 9 :: Views: 601
This is my CRC32 function which yeilds ff79a6f1 for '3B' as input. But, when I check for '3B' in this website it shows 0x630906A9 as CRC output. Why is this different from my output? If my function is not working correctly
PLD, SPLD, GAL, CPLD, FPGA Design :: 06-18-2016 13:03 :: rakeshk.r :: Replies: 0 :: Views: 719
bit addr, crc, data;
function void calc_crc;
crc = addr ^ data.xor;
function void display;
$display("Transaction: %h", addr);
$display(" Result CRC = %h", crc);
t = ne
ASIC Design Methodologies and Tools (Digital) :: 04-18-2016 05:47 :: anilineda :: Replies: 1 :: Views: 546
Hello, I'm using Questa Sim 10.0b for Test bench with System verilog and UVM. I did some examples and they works, but I have problems using DPI, in fact after writing my C function and importing it in Systemverilog code, when I compile get the following error:
"# ** Error: (sccom-95) Your installation directory does not contain the (...)
ASIC Design Methodologies and Tools (Digital) :: 04-07-2016 20:57 :: ireon :: Replies: 0 :: Views: 733
In my book (which exists inside my head), there is never a good reason to declare a function or task as static; that is a verilog oddity that we a stuck with for legacy code. Re-entrant routines are those that can multiple, simulations activations without one activation interfering with the state of another.
The only way you can have a re-entrant
ASIC Design Methodologies and Tools (Digital) :: 03-12-2016 19:20 :: dave_59 :: Replies: 9 :: Views: 780
At first sight, the code function can shortened as bcd = code, because it simply performs a bit-by-bit copy. But what did you want to achieve?
ASIC Design Methodologies and Tools (Digital) :: 01-20-2016 18:40 :: FvM :: Replies: 6 :: Views: 4373
I would like to communicate c with verilog. I find the verilog PLI can solve my problem. I read this website to learn
But I still can't work even a printf function. I use ncverilog for verilog compiler. What I done is below. I can't have a successful compile for this. It says that it
ASIC Design Methodologies and Tools (Digital) :: 12-24-2015 08:05 :: u24c02 :: Replies: 1 :: Views: 881
Because the do_copy function is declared virtual, it calls the version that is "lowest" in the inheritance order, which in this case is the do_copy function from the derived class.
This is quite important, for example, you had an array of base_class objects, which were all different child clases in reality (eg. derived_class1, derived_class2, deri
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-03-2015 11:39 :: TrickyDicky :: Replies: 3 :: Views: 974
i am trying to randomly generate values in system verilog using "randomize" function. But, the simulator VCS throws me the following error:
Error- Identifier not declared
Identifier 'randomize' has not been declared yet. If this error is not
expected, please check if you have set `default_nettype to none.
ASIC Design Methodologies and Tools (Digital) :: 11-18-2015 22:41 :: aamalathithan :: Replies: 2 :: Views: 941
I am confused about my BASYS2 FPGA board's common anode seven segment 4 digit display's function. In user manual(and also tested in verilog code), the desired digit is enabled when the anode is driven to 0(e.g. to enable the rightmost digit the bus should be 1110 each of which represents the anode signal, respectively), which doe
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-07-2015 16:49 :: Valerius :: Replies: 1 :: Views: 720