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278 Threads found on Function Verilog
Hi all, I am trying to do function verification using System verilog. I have DUT developed in verilog. The DUT is very complex. I would like to run multiple test on this DUT, from batch mode. The compilation and elaboration of the DUT takes long time in the whole simulation process. So I am wondering is there a way I can compile, (...)
Hi, I would like to generate a step function which will generate a stair signal. The code is following: if (count <=(stps-1) ) begin @(timer(period, period, time_tol)) begin x = x + (0.6/(stps-1)); count = count+1; end end else begin x = x; end But there are some sharp transitions which are creating convergence error,
module coding(clok,data,coded_out,out,rst); input data; input clok, rst; output coded_out; output out; genvar i; for(i=0;i<=4;i=i+1) begin sipo str1 (.din(data),.clk(clok),.dout(out),.reset(rst)); convol_enco u3 (.coded(coded_out),.in(data),.p_out(out));
Still there exist many bugs in Z-domain function of verilog-A. So I don't recommend use Z-domain function of verilog-A. Use "pllMMLib/z_integrator_digi".
pls help me i need verilog code for biphasic waveform generation This forum doesn't function in the way you think. Tell us about the design scenario. Describe the problems you are facing. What part of a the code you don't understand. Show us what you done! Members will help you in these aspects.
can any one help me how to implementation this function verilog modelsim VHDL f=W* W C N 4 bit N is radian hi, verilog modelsim VHDL whats that mean? if you are using verilog, re you able to use any ip cores or you need to design your self?? what is the format of the 'N', i mean h
I am prejudiced against using task (the only reason is because I have myself never used it and most legacy codes/cores do not use it). I remember using function once and it was synthesizable. In my opinion a clock is necessary. Since there is no clock, your use of blocking statements is justified But you can use tasks inside a clocked always
this does 3/2=1.5 instead of 3.3/2=1.65 and for 3.7: 4/2=2 instead of 3.7/2=1.85 Is this happening with the value displayed or the value effectively stored at the variable ? In other words, assuming that you're using the $Display function, are you using the correct formatter ?
You can use verilog-a for implementing this function.
Is this possible placing the if statement inside the genvar and for look because I want to check each element of an array zero or not ? And then assign specific function for the values if its zero or non-zero element? Because when I tried the above syntax its throwing an error "A is not a constant" ? Thanks genvar
In my experience, many company use below approach to design hardware by verilog/VHDL: 1/ Understand the requirement or the function of design. 2/ Describe the design in schematic or block diagram. It is not mandatory but it is better to make it closed to gate level ( AND, OR, NOT.. FF, RAM .) with connection. 3/ Write the
This is my CRC32 function which yeilds ff79a6f1 for '3B' as input. But, when I check for '3B' in this website it shows 0x630906A9 as CRC output. Why is this different from my output? If my function is not working correctly
class transaction; bit addr, crc, data; function void calc_crc; crc = addr ^ data.xor; endfunction function void display; $display("Transaction: %h", addr); $display(" Result CRC = %h", crc); endfunction endclass module test; transaction t; initial begin t = ne
Hello, I'm using Questa Sim 10.0b for Test bench with System verilog and UVM. I did some examples and they works, but I have problems using DPI, in fact after writing my C function and importing it in Systemverilog code, when I compile get the following error: "# ** Error: (sccom-95) Your installation directory does not contain the (...)
In my book (which exists inside my head), there is never a good reason to declare a function or task as static; that is a verilog oddity that we a stuck with for legacy code. Re-entrant routines are those that can multiple, simulations activations without one activation interfering with the state of another. The only way you can have a re-entrant
At first sight, the code function can shortened as bcd = code, because it simply performs a bit-by-bit copy. But what did you want to achieve?
I would like to communicate c with verilog. I find the verilog PLI can solve my problem. I read this website to learn But I still can't work even a printf function. I use ncverilog for verilog compiler. What I done is below. I can't have a successful compile for this. It says that it
Because the do_copy function is declared virtual, it calls the version that is "lowest" in the inheritance order, which in this case is the do_copy function from the derived class. This is quite important, for example, you had an array of base_class objects, which were all different child clases in reality (eg. derived_class1, derived_class2, deri
Hi, i am trying to randomly generate values in system verilog using "randomize" function. But, the simulator VCS throws me the following error: Error- Identifier not declared, 31 Identifier 'randomize' has not been declared yet. If this error is not expected, please check if you have set `default_nettype to none.
Hello everyone, I am confused about my BASYS2 FPGA board's common anode seven segment 4 digit display's function. In user manual(and also tested in verilog code), the desired digit is enabled when the anode is driven to 0(e.g. to enable the rightmost digit the bus should be 1110 each of which represents the anode signal, respectively), which doe

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