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I am new on PCB design. I want to learn, as I have no idea about how should I do my own designs, I am copying some existing ones .. So, I choose a Simple One, a Frequency Generator Module (XR-2206): 157392 The PCB Layout at the Top looks like this: 157393 and at the botton looks like th
I am new on PCB design
Anyone designed with Oceane?
Hi all, I'm working on a design that draws power through USB but needs about 1.5A of current at 5V. Hence I'm exceeding the 500mA limit and need to "negotiate" a higher current from the source. I've read various pieces of USB documentation and I understand a small microcontroller would be the way to do this properly. I'm looking for a solution t
I have a VCVS instance in my schematic design. I can't find VCVS in layout after generate from schematic because there is no VCVS PDK in Layout. How can solve this problem? Thanks. Attached is VCVS symbol in schematic.
Hi, I am trying to design a structure where I need to add some non-symmetric s parameters. However, HFSS is automatically converting it into symmetric. What should I do in this case. In the structure, I have created circuit port and add snp file which is not symmetric. but HFSS is automatically converting this into symmetric. In this case wha
Hi guys, I have a schematic of OTA amplifier: 157362 I want to know the W and L that were used to design this OTA. I don't have more information other than the ones provided in this picture. since all transistors are in saturation, I thought about using the saturation current equation to find (W/L) ratio. by assuming
I need a max of 40v and 8a to power my drop down variable power supply. I have old microwave transformers so I removed the secondary and rewound it with 14 gauge wire. I now get 48vac and when I use a bridge rectifier it brings it down to 40vdc. I tried to test amps by hooking up my tester (rated at 20amps) and only succeeded in burning up some jum
Dea Forum Im designing a FIR filter, in this case a low pass. I get the coefficients from Matlab (no matter from where..) ,that are from 0 to 1, in floating point. Now, I want to implement this FIR in my FPGA ,with buil in 18x18 multiplier. So,I transform the coefficient in integer value of max 17 bit (1 bit for sign) ,multipling the big
Hi I have found this filter/amp combination, being simple with nice features. I wonder can I use other opamps like the ne5534 or is the performance specific to the 741 and will differ if using other opamps? Also how about Jfet based ones like the tl071?
Hey all, I am using Verdi for simulation of RTL. We have lot of assertions in design and I would like to know if an assertion is fired in a simulation or not. There is a assertion debug mode which should list out all the assertions, however, I am not seeing any information if it is passing, failing, checked, or not at all fired. Is there some ki
Hi All, I have been working in a company for 3 years an a half as an electronic design engineer. I have done schematics, layout, test prototypes...etc. When I started to work there was a good number of product range already developed, so what I have done mainly is adding features to existing products rather than design product from scratch. I a
Hi All, I have been working in a company for 3 years an a half as an electronic design engineer. I have done schematics, layout, test prototypes...etc. When I started to work there was a good number of product range already developed, so what I have done mainly is adding features to existing products rather than design product from scratch. I a
Hi All, I have been working in a company for 3 years an a half as an electronic design engineer. I have done schematics, layout, test prototypes...etc. When I started to work there was a good number of product range already developed, so what I have done mainly is adding features to existing products rather than design product from scratch. I a
As a beginner to VSLI design, I am using and learning Innovus these days and have two questions. Hope someone could help me. 1) set_db. The user manual has some sample flows with codes. It usually contains 'set_db' commands to set values for some attributes (the manual calls it database object.) These object usually is the attributes belong to
So I want to see what are the input patterns of the design which has an output of stuck at 1 at the output named 'outtt' of my behavioral verilog code (of course which I later synthesized)...what should be the appropriate commands for tetramax for this? :?:
Hello, I am interested in learning about analog integrated circuit filters - Active RC, GM-C, OTA-C, Switched Capacitor filters. Can anyone recommend books for learning in this field, with numerous examples ? I like the Valkenberg Analog filter books and also the Laker and Sansen book. Any other books ? Any course notes or (...)
Hello everyone. Currently, Im designing a processing element. This design is synthesis in Xilinx ISE design Suite 14.7 using Virtex 6 XC6VLX75T-2FF484. I have problem on the timing analysis. The is no setup time and hold time reported as shown below. 157310 There is no slack for setup time and hold time. Durin
Can anybody please suggest me any resource on wireless power transfer coil design?
In a prototype board for Lithium battery charge control, I have a three input AND gate (74LS11N). The inputs to the AND gate are: 1A = 5/0 volts from a digital output pin on an Arduino nano 1B = drain of an N-channel MOSFET (HUF76423P3) acting as low side switch on a 5 volt supply 1C = drain of a P=channel MOSFET (STP10P6F6) acting as a