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154 Threads found on edaboard.com: Generate Timing
Hi All, I have to generate RGB signals from an application processor, having equivalent timing parameters for NTSC and PAL (Later this signal will be converted into an analog signal). By looking at the analog video signal (NTSC or PAL) how can we calculate the digital timing parameters ? I specifically need hback-porch, hfront-porch, (...)
Its much easier just to generate a single constraints file and include it with the design. The .sdc file is just a tcl file that allows you to run tcl commands (for altera at least), like applying sdc constraints only to the fitter if you really have to (for example overconstraining the design during the fit to try and make it meet timing during ti
You can generate variable pwm using one timer and one pot also. 1.make port pin ON. start timer with ON time period 2.when it expires load OFF time period to timing registers. And make port pin off Whenever ADC value gets changed calculate new ON, OFF values for timer registers
Hi All I am trying to speed up the ams simulator by using behavior model. However, the behavior model does not generate correct results. It seems to due to the timing problem. It used to have some .libs for ams simulator, but right now I only have fixed rising, falling time and delay in the behavior model. Can anyone comments on how to solve t
I am trying to build a Standard Cell Library and it's associated .LIB file. I have made finished making all the individual cells. Next step involves making a .LIB file with timing and power information. I am trying to find simulation setups to generate data for the required matrices to be included in the .LIB file.
Hello, I need help with NCO ip tool,vhdl code generated from quartus IP tool,and im trying to add this code in my project. could you please say,what should i put on phi_inc_i? U_cord_gen : entity work.cord_gen port map ( clk => clk, reset_n => not tx_reset, clken => clken, phi_inc_i => phi_inc_i, fs
Using clock as data and generate clocks as in your example is likely to cause timing problems. It would be helpful if you specify the problem completely, e.g. with a timing diagram.
I have extracted the def file of my processor in innovus/encounter/EDI and ported it to calibrewb in order to remove some dummy lines. Since calibre cannot generate def output, I saved the final design in oasis (.oas) format. Now I would like to import the oasis into cadence platform in order to extract spef files and do timing analysis. Anybody kn
This is a very complex question. The simple answer is that is it better to rely on static timing analysis tools to determine your critical paths - they are far more accurate. In dynamic simulation, you need assurance that all the models can accurately generate X's when there is a timing failure, and that the same models are written to (...)
What's the waveform you want to generate and where is it used for? People avoid generated clocks in FPGA design and use clock enable signals wherever possible.
try to generate the bram with core generator instead....
You run one of those tools, which run spice using the netlist for the standard cells, and then they generate the .lib for you.
In general I would expect DRC and Monte Carlo methods will determine critical timing and path length issues. Critical path (shortest latency) results should come out of a manual or auto generated set of test vectors in combinational and sequential table and generate the results which could be sorted. But I offer no step by step solution on each.
Hi, I have a design which uses MIG ip.I added some user modules & i could get it to implement successfully.But in that design,i had differential system clock & reference clock.(4 diff sys clk + 1 diff ref clock.) Earlier all these diff. clock inputs were inputs to my top module,now i wanted to generate those clocks internally by using cloc
I would try it out in this way... Using a counter and the 10MHz clk, generate a signal that is HIGH for 100ms and LOW for the next 100ms, that gives us 200ms. Use this signal as clk input to the stop_flag register.
Hi Electro ns, since SSI is a synchronous type of serial transfer and you generate the master clock it can be generated in software if you meet the timing of the device connected. The general SSI description can be found here: . There are some differences from MFG to MFG and you need to h
For a start I would never have known from your code that Timer 4 was working as a 16-bit timer but that Timer4/5 was not working as a 32-bit timer. This is why you need to explain what it working and what is not. The problem is that for 32-bit timers, the interrupts are generated from the 'odd' numbered timer (last bullet point in the "Timers" FRM
I want to generate 250Khz analog signals through microcontroller. I am going to use 2Mhz square wave with different duty cycles followed by low-pass filter. I have simulated all these things in simulink and getting square wave with variable frequency according to my requirement. The problem is i want to know the exact timing when square wave ch
is it possible to generate two or more timing signals (square) AT89S52 I want to generate two different timing signals in same time accurately :cry:
I used the clock divider to set the clock of the ADC (according to dataheet 4.8kHz) 4.8 kHz is the maximum sampling rate, not the clock frequency. The ADC clock frequency is generated by a crystal on the module. You'll generate a SPI interface timing according to the datasheet specification. Maximum SCLK frequency is 5 MHz, 1 or 2


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