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Hi, I am trying to import pspice .cir file into cadence spectre and I have successively generated the schematic graph. However, when I run the simulation, some errors appear. Here are the errors 157880 Here are the settings in schematic 15788115788215
Hi there, I wanted to know how to actually implement the P, I and D sections of of controllers in hardware? What is the actual electronic circuitry behind it? If possible pls. point me to a relevant textbook as well. Thanks and Regards, Arvind Gupta
Hello, I have designed simple voltage devider MOS resistor, the circuit is working fine in schematic, with the layout there is no issue, LVS is giving o error. However, in the simulation they are showing very different result, then when I compared the netlist I saw it is different between the schematic and layout, looks like he is mixing between
I want do simulate a diplexer with the axiem simulator. My problem is, that I also need to use a capacitor and a resistor in the design. This works well in the schematic simulation, but produces strange results with the axiem simulator. The S21 attenuation is much to high. I'm using models from the modelithics library. Another strange thing is, tha
Hello, I am designing a new PCB for LLC converter and I just finishend laying out the H-Bridge for the input section. The PCB is 4 layer and primary side is rated for 500V/6A. Switching freq. is around 100kHz. I used TO 247-4 MOSFETs for H-Bridge. I named positive input to HV+ and negative input as PGND. Switch nodes are also shown below. Furth
The test_se signal is connected to the TE pin of my ICG cell. I already issued the command set_dft_signal -view existing_dft -port test_se -type ScanEnable -active_state 1 -test_mode all but the tool still treats the value of the test_se port as X. 157557 157558
When one device has multiple antennas and some of them operate in the same band (like WIFI and Bluetooth), how can we lower the coupling between two closely placed antennas? Is there any rule of thumb for antenna layout or grounding?
Hi there, As I know, the command to create Interface Logic Model (ILM) create_ilm in ICCompiler 2017 version was obsolete. Do you know that is there equivalent command to substitute for create_ilm, or the functions of ILM are completely removed and are already included in CEL view an FRAM view? Thank you
Good day everyone! I need your help on this one. I'd like to derive the equation for the closed-loop input impedance of the circuit attached. The final form of the equation is also shown below. 157314 157313 Here's what I have tried 157316 I was stuck. Can you tell w
Hi, I am looking for Mentor compatible footprint or cell for the following two 1- SDRAM - MT41K256M16 and 2- Flash - S25FL127S. How to find ?
Can the momentum simulation results be better than the simulation result of the schematic?
Hi, From the view of antenna theory, beam forming means using multiple antennas to create a desired beam, or controlling the beam direction by changing the magnitude and phase of each antenna element. Usually we'll regard all the elements as one antenna when we look at the far field. In communication theory, MIMO means utilizing diversity to
Hi there, I wanted to know what all is there to know about synthesis of HDLs pls. I recently went to an interview and I was told that I don?t know anything about synthesis (I basically knew what synthesis in HDLs mean and could only translate simple behavioral models in logic gate circuits). Hence pls. tell me what all to know about synthes
Hi All, I need to view the assertion pass/ fail/ vacuous pass status in the Questa Waveform Window. Which switches do I need to use with the vsim command for this purpose? I am using -assertdebug, -voptargs=+acc, -msgmode both in my vsim command as of now. I am able to view the failures but not the pass/vacuous pass. Can anyone please help me wi
Hi all~ I'm trying to simulate the phase noise of my VCO and I used EM simulator to extract port to port s-parameters (all ports including IND and MOS,,...) and applied the results to cadence schematics through nport in analogLib. PSS/Pnoise results of phase noise in cadence was so bad and it shows difference of more than 10dBc/Hz compared t
Dear Friends, I finished with the design of single ended OTA. the GBW was achieved is 20 MHz by driving capacitive load of 10 PF. Now I chnaged the design to fully differential OTA and I kept exactly the same biasing current or circuit transistor ratios, then I connected the smae load of 10 PF differentially between the two outputs to make a com
Hello , how to generate proper layout from this schematic ? i need to make layout so i can export the gerber file. Note : Both are the same just rearranged. 156729156730
For many years, I have seen support questions and forums posts where new Momentum users made mistakes related to the emModel view. If you use Momentum and don?t know what the emModel view is, this appnote is for you. It will help you to use Momentum results more efficiently in circuit simulations.
Dear friends, I understand for the wide swing mirror we need cascode diode biasing voltage like the one seen below, no doubt about it 156697 However, for the following fully differential circuit shown below, the common mode feedback circuit as you see is using cascoding diode to bias single transistor (M3&M31 gate)
long story short: making pwm motor driver circuit for as apart of my senior design project, trying to get TI's DRV8874 transient model to simulate inside of orcad. I believe I followed all of the info in the data sheet and it's not reacting to anything. Also, im fairly sure i imported the model correctly, imported the orcad file then tied library f