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error message was displayed that communication time out. Is your software registered? Is your module registered? getting success until the crucial moment, then a strange error message appearing might be their way of blocking unregistered software or hardware.
Hi, I am trying to read in UPF at RTL level. For the all standard Cells, Memories, Analog Macros - Power config file is used to add search path and db file name. I have the below two observations - 1- After adding power config file, I have removed the corresponding RTL files of standard Cells, Memories, Analog Macros from file list. Aft
I designed a voltage doubler rectenna using qucsstudio free simulation tool. Since it is a bit more manual than ADS (with equally amazing capabilities nonetheless), there is need for extra input on the data display in terms of syntax to give you the graph you need. I have obtained the S11 and S21 plots of the rectenna but am struggling with getting
I am using launchpad board "TMS320F28069M ". While loading the program to the TMS320F28069M microcontroller there is no issue, but while debugging the program, it shows rise in temperature. We checked for the temperature of the controller and it shows around 40 - 45 degree Celsius. The same phenomenon is observed in our self made circuit board(usi
I don't see a specific reason in the code for getting outliers in the first channel. Determining the absolute maximum of instantaneous voltage is however a poor method to measure AC voltage. A simple reason might be that the input voltage is actually distorted, or there can be crosstalk on the PCB. I would try with a low pass filter, e.g. 10
You are getting things wrong. You use the pattern generated by Tetramax to run simulation. VCS is just a simulation tool which uses this generated pattern and feeds them to your design. Use VCS for simulation. I think you should read the user guide thoroughly.
Thanks Shalin. The below update has been done in SGDC, it helped in shift violations but not in capture violations. Still I am getting violations in Capture - "Reset/Set to XXX flops is not controlled in Capture Mode" Reset Scheme is as below - IO --> PAD --> Scan Mux --> Flop Now I have defined the constraints as below
I am trying to get the value of the h field with a horn antenna as a reference antenna. I used a 90 degrees waveguide twist with the horn antenna in preset to measure le level of the received signal. But I am getting strange values. Am I proceeding the right way to measure the h field? If yes is it a scaling issue if the values that I?ve got? I
Hello, I am trying to design a split ring resonator and extract the material properties. But before doing that I thought it's a good check what my simulation gives me for known material. I selected Teflon as my material and design floquet port in order to extract the material properties like permitivity over the frequency range. However, I am n
You are missing the point of how this forum works. 1) you can get help with understanding the theory of something 2) you can get help fixing problems with your code or code you got from somewhere else 3) you can get help with how to debug something you've built or debugging a specific issue. 4) other questions involving something you've worked on
Hi I am using FMC150 Daughter card which has 14 bit TI ADC which can be configured for both LVDS and LVCMOS type output to carrier card. When I am setting the adc in LVCMOS mode with 2's complement digital output, I am having the output bits raised by 2^13. So my output is always in unsigned mode with DC bias of 2^13. If I am giving no input signal
Hi guys, I designed a PLL, and I'm not getting to a locking state yet. I'm trying to debug the problem by observing the behavior of different signals. It seems that I'm getting only Up Pulses and the behavior is periodic. here is one that simulation that shows the periodic behavior of Up pulses: 157210 [ATT
Can simulator like ncverilog simulates the metastability behavior of CDC circuits? How to do simulations with metastability models (RTL and gate-level)?
What do you mean your “transreceiver is getting short-circuited most of the time”? That’s not very descriptive. Is there zero resistance across the power supply pins? Does the device get very hot and fail?
Hi, I am designing a differential folded cascode with both P and N-mos input transistor stages due to my different input common modes. During my transient analysis while running across the corners i am getting some offset of 70mv at worst between the two outputs. How can i minimize this offset. Note: I am giving a 0.3mV offset at the input an
I have been using ADP5070 DC-to-DC Switching Regulator with Independent Positive and Negative Outputs to convert +5v to +/-15V. Upon testing on the PCB, Desired Outputs are +15V and -15V on the independent boost and inverting outputs of the ADP5070 ic respectively. Outputs we are getting upon testing are +15V and +13.8V respectively. I have done
I have been using ADP5070 DC-to-DC Switching Regulator with Independent Positive and Negative Outputs to convert +5v to +/-15V. Upon testing on the PCB, Desired Outputs are +15V and -15V on the independent boost and inverting outputs of the ADP5070 ic respectively. Outputs we are getting upon testing are +15V and +13.8V respectively. I have don
It is unlikely that any FinFET foundry has released these to anyone without a NDA, and very likely that the models are encrypted. That being said, you might find at least I-V curves and maybe fmax / fT numbers that could let you fit a model "well enough" for whatever you're about. Since that evidently does not include having a real foundry
Hi, I have an AC source where I want to connect it to LTC1966 to measure RMS voltage. 1. I am not getting the expected output. Can I use a battery (5V) as the supply voltage and connect my AC source to IN1 and IN2 of LTC1966 (no common gr
c_mitra is correct, the integral should be over a full cycle 0 to 2 pi, or -pi to pi or ... for signals other than sin, replace 5 sin(theta) with the appropriate other function the pi (should be 2 pi over a full cycle) in the denominator is from integral with same limits as integral in numerator, but the argument