78 Threads found on edaboard.com: Global Power
Same comment as Klaus.
Reputable capacitor manufacturers will provide ripple current limit values somewhere in the datasheet.
Sometimes the value is not found on the individual capacitor datasheet but as a global family specification.
Power Electronics :: 07-13-2016 18:36 :: schmitt trigger :: Replies: 3 :: Views: 552
Hi,
Packman style... The faster the computer the the faster the 5 seconds.
In some years the 5 seconds will be only parts of seconds.
Additionally it needs a lot of processing power.
****
I'd go for a timer.
Define a global integer variable "to"
Timer with 100ms timeout.
On every timer event decrease "to" until it is zero.
Within your key rout
Microcontrollers :: 12-22-2015 20:59 :: KlausST :: Replies: 3 :: Views: 625
It is common to use microinverters with a rated capacity lower than the solar panel they connect with.
Power Electronics :: 11-17-2015 01:44 :: E-design :: Replies: 2 :: Views: 461
hello
on GSM M95 (QUECTEL ?)
after global init :
* STAT must be =1 (status of power ON)
* NET info must blink
GSM must give response when sending "AT" command =>"OK" means UART speed OK
send PIN code "1234" ?
and test presence of network
20:01:44.125> Test si enregistré sur le reseau (AT+CREG?) // send AT
Microcontrollers :: 11-03-2015 09:40 :: paulfjujo :: Replies: 3 :: Views: 635
Hello
I have some questions about calibre LVS.
I am trying to do LVS to mixed signal IC (analog circuit + Digital circuit).
as for digital circuit, there are some global nets (VDD! , PSUB!and VSS!).
I'd like to use it as VDD!=DVDD, VSS!=DGND and PSUB!=GND on TOP level.
do you know how to run the LVS? I don't know how to do it.
rega
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 09-28-2015 23:07 :: Clark masa :: Replies: 3 :: Views: 2753
Uncertainty for global margin. Don't add uncertainty globally though if you have a few tricky paths, as this will increase area and power, and make it harder to fix, use set_path_margin on the specific paths.
ASIC Design Methodologies and Tools (Digital) :: 09-28-2015 09:17 :: jbeniston :: Replies: 1 :: Views: 606
Hello,
We have a design requirement for a power PC based ASIC. Due to our existing relations with ASIC foundries, we can't directly license it from IBM/global foundaries.
Could you please suggest who can provide soft cores for PPC405 and its surrounding sub systems ( like PLB , OPB, EPB etc components)
I have checked with couple of vend
ASIC Design Methodologies and Tools (Digital) :: 06-17-2015 21:38 :: blorecheckan :: Replies: 1 :: Views: 802
Hi,
as we know there are two types of routing tech we follow while designing the chip. 1) global routing. 2) Detailed routing.
The goal of the global routing is to route as many nets as possible while meeting the capacity constraints of each edge and any other constraints if possible.
While in detailed routing , we decides actual physical interc
ASIC Design Methodologies and Tools (Digital) :: 04-09-2015 14:47 :: vikramrajput :: Replies: 1 :: Views: 692
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Business, Promotions, Advertising :: 03-06-2015 06:05 :: HundaSunny :: Replies: 0 :: Views: 544
Hai friends,
I have created a heterogeneous component into 8 parts each consist of 3 pins.
in that first 4 parts has one common pin called ground 1 ,
the next 4 parts also has the one common pin called ground 19.
so i have decided to assign the first part into 3 pins the other 3 parts into 2 pins structure by removing the ground pins..
whi
PCB Routing Schematic Layout software and Simulation :: 01-21-2015 04:05 :: TADE :: Replies: 0 :: Views: 1008
A few possibilities I see:
1. Port configuration may not be correct.
2. The compiler disables global interrupt in timer ISR entry. Hence while you are sleeping in ISR, interrupt not forwarded to software.
Microcontrollers :: 07-12-2014 04:08 :: nitrojacob :: Replies: 2 :: Views: 979
Got vega 650 power supply. Any idea on how to power up. I saw one of the primary option is FV (AC Fail, global/fan Inhibit, 5V/300mA standby). What does it mean? Please help me understand and help me power up...thanks a lot. See attached photo for more info...thanks again.
106198
Power Electronics :: 06-11-2014 04:08 :: RHeTTRoNiCS :: Replies: 0 :: Views: 904
Hi
I am a digital guy. When I am testing our chip in the lab. I found a weird thing
The chip is just power up, the most up stream block is output constant signal by default. We didn't do any configuration at all.
The weird thing is when I apply a global reset to digital core (hold reset to be always active), I found total power goes (...)
Analog Circuit Design :: 05-31-2014 06:45 :: wy21century :: Replies: 5 :: Views: 835
Hi,
I have a hierarchical style design-which means power ports are global.
I'm getting the duplicate net names on one of my power ports (not all of them-just the one). And I'm not sure why?
Its a custom port-but so are my other ports. What would make a port throw this error?
Thanks.
as nodes they all are th
PCB Routing Schematic Layout software and Simulation :: 05-08-2014 18:53 :: zeyad.kassaby :: Replies: 1 :: Views: 1760
Hi Everyone,
Design: I have 2 decoder written in Verilog, and a test bench to generate the decoder input and clock.
I have imported all the 3 modules separately and created a schematic view and config view. I have also declared global power supply in the design.
I have verified the decoder separately for its functionality using ideal voltage
Software Problems, Hints and Reviews :: 12-04-2013 09:19 :: aarthy_maya :: Replies: 0 :: Views: 617
Hello
My global variables are only initializing to defined values when i download my code to LPC2468. After power reset my global variables are initializing to random values. I am getting following warning :
.\Obj\ethernet_bootloader.sct(8): warning: L6314W: No section matches pattern *(InRoot$$Sections).
My scatter file :
; *
Embedded Linux and Real-Time Operating Systems (RTOS) :: 09-19-2013 10:34 :: niketrc :: Replies: 0 :: Views: 1684
Hi,
I have given a project in which I need to design an ADC for GNSS (global Navigation Satellite System). Here are some of specifications of the ADC.
input frequency fin = 20MHz
Bandwidth = 20MHz
power consumption P <= 1mW
ENOB >= 3.7
Resolution: 4 bits
I am confused which sampling frequency should I choose?
Analog Circuit Design :: 07-09-2013 09:11 :: Osawa_Odessa :: Replies: 0 :: Views: 500
The verilog netlist has this statement for instantiating fillers:
FILLERD1TD FILLER_323334();
FILLERC4TD FILLER_323334();
The cell FILLERD1TD has a symbol view only as its a pass through, but FILLERC4TD has a symbol and a schematic as it is has some moscaps. Both symbols do not have any pins as the power and grounds are globals in the CDL netl
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 06-15-2013 00:35 :: snfvsd :: Replies: 0 :: Views: 1021
Hello,
I am trying to do the power routing of the IO pads in my design. I connected all the power and ground pins using global net connect command.
globalNetConnect vdd -type pgpin -pin {vdd} -inst * -module {}
globalNetConnect vdd -type pgpin -pin {vdds} -inst * -module {} (...)
ASIC Design Methodologies and Tools (Digital) :: 05-21-2013 08:09 :: a_mythpi :: Replies: 0 :: Views: 999
Actually there are bunch of things which determine the clock tree power
a) Low Vt will consume higher power. For high frequency designs low Vt cells should be used for clock tree.
global clock tree should be preplanned with the number of buffers/inverters you need to use. Local can be a bit random ( read CTS tool fo
ASIC Design Methodologies and Tools (Digital) :: 03-21-2013 05:18 :: Prashanthanilm :: Replies: 5 :: Views: 1313