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15 Threads found on edaboard.com: Global Setup
Hi I have designed a sequential cell that computes a logic function. I want to use this cell as combinational cell because both its clock and data are generated independently (there is no global clock). Therefore I am using data-to-data setup check in RTL compiler. I am able to let the tool know that such checks should be performed (i.e. "cloc
It's on PORTB. 1.) Run init function to setup global interrupts 2.) Write interrupt
Can you post a better pic of your structure? You can change the mesh density in "global mesh settings".
Hi gone Do you set initial condition in HSPICE? Check your power setup global vdd!, gnd! also. It should work
Hspice usually prints or plots just the voltages/currents (or whatever) which you specify within an appropriate .PRINT / .PLOT command. If you get all nodes' values, there's probably a menu field in your GUI setup, which says so, e.g. top_level, global, all (nodes). This is the way how it's done in C@dence' ADE tool, at least for [I
Its quite simple... Here is the sample code follows... Timer setup for PWM in c; //global variables and definition #define PWMPIN P1_0 unsigned char pwm_width; bit pwm_flag = 0; void pwm_setup() { EA = 0; TMOD = 0; pwm_width = 160; TR0 = 1; ET0 = 1; EA = 1; } Interrupt Service (...)
hi, I completed the CTS, my setup and hold are positive...but the global skew is negitive. what might be the problem and what will happen if the global skew is not met for my design after meeting setup and hold? thanks
i've that book... i want to know about useful skew,local skew ,global skew and all those things..it's not given in this book Dear Biku, useful skew:- This is the min skew required to meet both setup and hold violations of a path. Sometimes, what happens, when we try to meet setup with skew=0(practically 0 skew is not possible) th
Hi, Can anyone tell me the significance of global skew? Regards,
Hi i have a design which has a lot of Hold errors due to a very high skew in a clk which is routed through a BUFG. The FFs has cross clock domains but this global clock skew is causing the hold errors. How can i solve this. Does a BUFR on A BUFG help.? if so will tool identify the right bufr or sdh i direct it according ? Thanks in advance
did you mean .bashrc as below: # .bashrc # User specific aliases and functions alias rm='rm -i' alias cp='cp -i' alias mv='mv -i' # Source global definitions if ; then . /etc/bashrc fi CDSDIR=/tools/IC5 CDS_ROOT=/tools/IC5 CDS_INST_DIR=/tools/IC5 CDS_INSTALL_DIR=/tools/IC5/tools/dfII/ export CDS_LIC_FILE=$CD
You can try the 'fix opt global' command, it is used after placement or CTS to fix setup timing. Best Regard
Hi setup time and hold time calculation is same as in flip flop but in case of clock gating it will different.. suppose there is single flip flop and u r doing clock gating(some combinational logic is added at input of F/F ) then global setup time will increase and global hold time will decrease .. Regards
Hi binu george, it is not possible to avoid that error it occurs if any illegal type of work is done in the design but the design can be retrived from the backup file location specified in the setup-->PREFERENCES-->global TAB
try this: setup--->preferenes-->global-->select "active layer comes to front"