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High Speed Sigma Delta

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21 Threads found on edaboard.com: High Speed Sigma Delta
I need help regarding a 5th Order sigma delta ADC design .. CLK = 384 Mega Hz ... what is the most suitable type of to implement the feedback DAC ? as i already tried the most simple structure and it's not working good with this high speed CLK ... i read about 'current steering DAC ' for example , is it suitable and (...)
To choose the architecture, it's all about trade-off. There is no "best" architecture. OSR - filter order - number of bit for the quantizer - continous time vs switched-cap... Each architecture has advantanges and drawbacks. It depends what you expect from you design : high accuracy ? high-speed ? low-power ?
I'm working on the sigma delta modulator, and I would like to extract the dynamic Performances like SNR, SNDR, SFDR.... I would like adapt maxim program for Dynamic Testing of high-speed ADCs to my work,(Selecting the Optimum Test Tones and Test Equipment for Successful high-speed ADC Sin
Why sigma-delta A/D converters are mainly dedicated to high-speed applications which can tolerate offset and gain errors? Thanks!
hi sandhaajith, the offset and hysteresis requirements of the comparator in sigma-delta modulator is relaxed and the high-speed is required, so it can be designed with a preamplifier followed by a latch with reset. see this paper: ?A high-speed CMOS Comparator with 8-b Resolution,? (...)
Schoofs R., Steyaert M., Sansen W., "Analysis of Gm G and RC filters for high-speed continuous time sigma-delta A/D conversion", in proceedings of International Symposium on Signals, Systems, and Electronics, Linz, Austria, August, 2004 Thanks
Audio:high resolution low speed->delta sigma ADC Video:high speed median resolution->Pipeline ADC
well in analog may be PLL or high speed data converters on FPGA DSP
there are some books and thesis they are good, i think book Top Down Design of high Performance sigma delta Modulators-Medeiro-1999 DeIta-sigma Data Converters-Norsworthy Understanding delta-sigma Data Converters(Temes) thesis high-speed, Low-Power (...)
hi all, i have a question about sigma-delta modulator architecture selection. someone tell me that using cascaded modulator when designing low osr and wideband, using single-loop modulator when designing high resolution and low-speed. this is right? thanks advanced!
search the following: continuous-time delta-sigma modulators for high-speed a/d conversion: theory, practice and fundamental performance limits by james A. cherry one of the very first books discussing ct dsm and many theories and issues were firstly discussed and studied in this book; actually u only need to download (...)
To achieve 6bit/560M character, my suggestion is to select pipeline structure, since your design is neigher high-speed(flash is suggested) nor high resolution(sigma delta is suggested). Best regards, hi i need to design the ADC for UWB transreceiver... the spec of adc is 6 bit resolution and the (...)
Does anyone has the electronic version of the following book: "Continuous-Time delta-sigma Modulators for high-speed A/D Conversion : Theory, Practice and Fundamental Performance Limits " ? which is valued on Amazon $200. I searched the books download of this forum, but no match. Thanks for anyone who can give a clue.
I have a project of 20kHz 12(or 14)Bit DAC. Do i need to use R-2R architecture to design it? And who can give me some advice or papers of this kind of DAC design. Thanks a lot!!
It is really not an easy answer: it really depends on the ADC accuracy (not resolution!), output data rate and cost effectiveness. For high accuracy (over 16-bit) low speed sensor application ADCs, I will favour sigma-delta ADC. But if it is only 10~12 bit range, then SAR ADC has a better chance. Keep in mind that sensor (...)
Hello all, Do you have any idea what's the highest sampling rate a delta sigma adc can achieve in today's state of art? 100MHz? 200MHz? 500MHz? Thanks!
Does anyone have this paper : O. Shoaei. "Continuous-Time delta-sigma A/D Converters for high speed Applications". PhD thesis, Carleton University, Ottawa, Canada, 1995.
Is there anybody who can tell me how to determine the minimum gain in two order sigma delta ADC.
"Principles of data conversion system design" Behzad Razavi You can find some books in the ebook board of this forum. There are many IEEE theses about AD and DA. You should make sure your interest about AD and DA is in which type . high speed or high precision. AD include flash, pipeline, sigma-delta, (...)
i think both pipeline and folding are qualified for this. but if it is 200MSBP , is sigma-delta practical under 0.18tech? sigma delta is not practical due to the high clock frequency that is needed. Only pipeline or folding. Bastos