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47 Threads found on High Voltage Layout
Assuming all other parameters are met (voltage, capacitance, etc.) there's no reason you can't use a larger footprint, unless this is a very high frequency design where size might matter.
First thing that have to look in those high-power failures, is the PCB layout. Second have to look to the power supply (bias) filtering and decoupling, and any unwanted coupling between high power components.
Hi, I assume high voltage spikes cause the fail. (Caused by wiring and stray inductance) Therefore we need to see your PCB layout. GND plane. Urgent for high speed high current switching. And there is no capacitor at 12V line. You need at least one low ESR bulk capacitor and I recommend an additional fast (...)
It is easy to reduce noise say on 50mV SMPS ripple using LC filter to desired level combined with PSRR on chip. CM and DM ferrite beads can also reduce ingress on high impedance inputs, if the layout causes crosstalk. I have used SMPS for video amplifiers and AMLCD bias without noise effects, but with care. In this case I stepped down 9V to 5V
what is switching frequency, maybe it is too high for igbt? Is your layout good? If not then noise will happen, and yes at higher voltage it would be probably more. But i dont know what you say, because do you mean your inverter doesnt work when your bus is 400vdc, or do you mean you cannot produce the 400vdc? What is you (...)
Hi, generally not, as long as you are sure you are within the specification of the MOSFET. But in reality this is hard to ensure without any protection, because any load inductance or even stray inductance causes high voltage peaks. --> It depends on the load, on the wiring and on the PCB layout. Klaus
Hi all, I am using the high voltage NMOS from the ams h35 process in my circuit. i am currently doing the layout. I was not sure about the connections to the RPTUB isolation around the DNTUB of this NMOS. Has anybody worked with this design kit and in particular , the high voltage NMOS from this PDK before? (...)
Did you watch the IGBT waveforms at lower DC input voltage, e.g. 600V? 18V gate voltage sounds a bit high, do you have TVS diodes near the IGBT? Failure at moderate output currents suggests massive circuit overvoltages due to bad circuit layout or missing input bus capacitor. Gate resistors above some 10 (...)
I was a high voltage spark generator for one winter. I bought some high quality Name Brand shoes that used synthetic leather for the soles so they have long tread life. When the humidity was low and I walked on a carpet I generated a whopping high voltage arc when I got near an electrical device that was (...)
I see a lot of problems with this design from dI/dt coupling, conductive losses on traces, no short circuit :sad: withstanding p rotection, no high voltage(3kV isolation from arcing. Start over using busbars with common mode paths on opposite sides of insuator yet high voltage insulation with 1kA surge capability.
I am using a multimeter to check outputs The most likely explanation is a high frequent oscillation of the amplifier, e.g. due to unsuitable circuit layout. You should check with oscilloscope. - - - Updated - - - Although LM8272 is specified to operate with inifinite load capacitance, the
A 12V to high voltage inverter is likely to cause considerable interference on the supply line and I suspect your ADC is reading that and getting wrong information about the state of the battery. When it decides to turn the lamp off, the interference is removed and the lamp tries to turn on again, it gets into an oscillating circle. First, confir
For low voltage signals a 90 degree route is fine. For high voltage layers a 45 is a must.
The unused (D0-D3) pins of the LCD should be tied high or left disconnected for 4-bit operation, not tied low as suggested earlier. I suspect the real problem here is the layout and lack of decoupling capacitors are causing the clock to act erraticly and the voltage regulator to oscillate. Connect a 10uF capacitor across the input pin and (...)
Hi all, Given a millimeter-wave multi-stage common source/cascode CMOS amplifier. Which method would be the proper design: inter-stage conjugate matching or resonance load (adjacent stage should be place close in the layout)? For CMOS transistor, it is gate-source voltage controlled device, it is more important to provide high (...)
ok, one by one: Silkscreen is the layer which contains whatever markings you want to have on your board (like, component designators, component orientation hints, high voltage warnings, hints for troubleshooting (eg.g 'this should be at 1.23345V' ), wild african animal pictures, design revision number, website, your name, basically whatever you li
Looking at the spec sheet for the smcj 30ca, it should clamp at about 30V with a max of 48 V at 50 Amps through it. How come a transient 2KV for 50nS, gave a 250 DC output?? With these short pulses and very high peak currents, the layout is very important else you get ringing on what is supposed to be an earth track. How do you know that your CRO
What are the additional layout guidelines we need to take care while doing a high voltage IC layout design. If possible kindly send some links regarding this topic. Regards Sreehari
all of them (ldmos, vdmos and demos) can be used as high voltage mos. Generally, >5V can be regarded as high voltage mos.
Boosting from 12V to 300V by conventional Boost may lower your conversion efficiency as you will be using an 500V FET for Boost switch (getting lower RDs on in high voltage is costly & there is an practical limit), but in isolated pushpull you still can use low voltage FET such as 40V or 60V depending on your design, leakage, (...)

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