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97 Threads found on edaboard.com: Hold And Setup Violations
Hi, how to fix setup and hold on same path, if we fix hold increase setup violation, and if we fix setup increase hold violation.
If clock latency is the difference in clock arrival at a particular flop compared to the clock source then why do we even care about latency. for eg : if skew is 0 at latency 500 ps (500ps for both launch flop and capture flop) then why would it even factor in setup or hold violations since it is the same for both flops. (...)
Can I always set false path for violation occurring at inter-clock-path ? ( provided , CDC is taken care in RTL ) Yes. How to solve Intra-clock-path timing violations ( setup and hold ) Provided that you follow good FPGA design practices (mainly using dedicated clock routes) - hold time (...)
Hi frinds.. after post Route fixing setup/hold still i'm seeing some transition violation and fanout violations how to fix them , what are the violations are real....? here are the Fanoutviolation info... ---------------------------------------- *info: there are 121 max fanout load (...)
Hi All Is there any special commands for fixing setup and hold violations after post Route. optDesign doesn't looks good and it couldn't optimize the design. so I think I have to use setOptMode to set some values.. But I dont know the exact parameters. Can anyone Please (...)
Hello all, I have 2 questions here setup and hold violations in same path - yes / no ? setup and hold violations on the same flop - yes / no ? I have know that setup and hold (...)
Hi everyone, I am doing P&R for a design and would like to use some specified cells (bufs/invs) to add into the path with hold violations. However, I am not sure how to implement this? Can anyone give me some suggestions? Thanks a lot, Tom
Better increase uncertainty. Because, increasing clock frequency will not issue any new hold violations (hold is freq. independent). But uncertainty will affect both: setup and hold.
Why do we fix set up violations in pre CTS stage and hold violations after CTS?
can any one expline me, how to find the causes of setup violation and hold violation because of cross talk. How to figure it out practically means in timing report we will see all the delay based analysis report but it also SI aware was true. But in the report how can i know the violation caused by SI. Thanks,
Well the tool will identify the buffers using function statement in the .libs. So any function A=Y will be considered as buffer. You can use eco_opt_design -hold to fix the hold times. I am assuming you will be adding parasitics and other other design rule constraints to EDI interface.
Hi all, in my design after CTS, i have 132 hold violations, and 100 setup violations. how do i can fix with help of ECO. i'm new to ECO. please help me to write ECO script for setup or hold. thank you..
there should not be any setup/hold/recovery/removal/transition violations present in design , input will be constraint file and post layout netlist , output will be your generated reports.
How to resolve hold and setup violations during Silicon Testing on Test floor.
worst case, means the lowest speed for the element, so if you reach your target frequency in this corner your design will reach at least the same frequency in the best corner (fastest speed). For the hold time, below 130nm, it is better to check the hold time in best and worst corners. In 65nm we saw hold time issue when (...)
The asynchronous reset must be released synchronous to clock to avoid timing violations and among other issues metastable states. Similarly all inputs to the synchronous process must keep setup and hold timing requirements. Using an reset signal with unrelated timing in a synchronous process won't be (...)
The library timing defined the timing table with two axes: the output capacitance and the input transition, and also indicates max trans/cap for each pins, this value could be the limit of the axes, or smaller (not really good if this is higher than the axes). The max capacitance and max transition violations only indicate (...)
Hello all, Which violation has to give more importance setup , hold or transition comparatively?
The basic questions will be on 1. Clock constraints (master clock, generated clock, clock skew, jitter, clock network delay, source delay) 2. Input and output constraints 3. Virtual clock and the use of it 4. False path and multi cycle path. How will you identify them. 5. How will you fix setup and (...)
Used STA tool to do eco fixing, and it will report the cell needed to fix the timing issue. But the first question, are you able to fix the hold after CTS or/and after routing?