333 Threads found on edaboard.com: Hold Time And Setup Time
how can i design a D flip flop and calculate setup and hold time for it?
Is there possible design d flip flop with PSSL family of logic ?
thanks in advanced
ASIC Design Methodologies and Tools (Digital) :: 04-02-2017 18:29 :: fateme_ayat :: Replies: 4 :: Views: 742
I would like to know how does clock latency affect setup and hold time? Does it help in any way?
ASIC Design Methodologies and Tools (Digital) :: 02-28-2017 20:02 :: shweta.bphc :: Replies: 2 :: Views: 658
I'm just referring a processor is a 33MHz rated part.
The AC Characteristics for 33MHz part tell CLK can be from 8MHz to 33MHz
and is further specifying databus setup time as 5ns minimum.
I have doubt if i provide the processor with 12MHz clock will the setup time (...)
Microcontrollers :: 02-02-2017 12:53 :: ku637 :: Replies: 3 :: Views: 692
I am about to find the setup time value for Virtex-5 FPGA (XC5VLX50T) and have looked at page 45 of the following datasheet:
it provides lots of timing values except the setup time value !! I know that hold (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-02-2017 01:26 :: msdarvishi :: Replies: 1 :: Views: 489
Can I always set false path for violation occurring at inter-clock-path ? ( provided , CDC is taken care in RTL )
How to solve Intra-clock-path timing violations ( setup and hold )
Provided that you follow good FPGA design practices (mainly using dedicated clock routes) - hold time (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-24-2016 10:00 :: shaiko :: Replies: 2 :: Views: 2839
if you have a path where two registers use the same clock enable that is a periodic clock enable, then you know that the setup and hold time can be much longer for these registers as they really only get updated once every N clocks.
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-18-2016 11:06 :: TrickyDicky :: Replies: 5 :: Views: 557
A circuit an timing diagram would be needed to understand your problem. If setup and hold time violation can not be avoided(asychronous incoming signals) a synchronization with two flipflops in series could be used. The second flipflop uses a delayed clock, so that metastable states of the (...)
Elementary Electronic Questions :: 09-24-2016 09:18 :: HTA :: Replies: 2 :: Views: 649
The set up and hold times of a FF are function of clock transition time and input transition times. What is the relation actually?? It seems the setup and hold (...)
ASIC Design Methodologies and Tools (Digital) :: 09-01-2016 13:34 :: biju4u90 :: Replies: 1 :: Views: 1110
As I know basically, in synthesis, we can get the information which is WNS,TNS, from start point to end point critical data path from synthesis schematic.
Also mostly in initial synthesis, we focus/concentrate on the setup violation because the hold violation is changed from CTS flow and P&R flow.
But I'm confused that the effect (...)
ASIC Design Methodologies and Tools (Digital) :: 03-17-2016 15:21 :: u24c02 :: Replies: 0 :: Views: 898
If setup and hold times exceed designed wait times, errors can occur.
But this is only one of a dozen or more mechanisms that can influence SNR and BER.
Many different algorithms to determine optimal settings or reliability have different tradeoffs for (...)
ASIC Design Methodologies and Tools (Digital) :: 12-17-2015 06:50 :: SunnySkyguy :: Replies: 1 :: Views: 938
How crosstalk impact the values of setup and hold time ?
ASIC Design Methodologies and Tools (Digital) :: 10-05-2015 10:59 :: cyrax747 :: Replies: 2 :: Views: 1747
Hi, recently I tried to simulate d-flip flop in HSPICE. I follow steps from this website ( ). I try to implement it in my netlist and it worked except for hold rise. I cant figure what's the problem, is it my code or the d-flip flop is acting weird.
Here's the screenshot of the waveforms:
ASIC Design Methodologies and Tools (Digital) :: 09-02-2015 21:07 :: xyy :: Replies: 3 :: Views: 1970
A Flip Flop is made up of master latch and a slave latch.
setup time: We need to provide enough time for the input capacitance of Master latch to be charged up or discharged down, before the Master latch captures the data. To ensure that this happens ,we have a setup (...)
ASIC Design Methodologies and Tools (Digital) :: 07-29-2015 05:02 :: shobhit :: Replies: 7 :: Views: 1016
Yes, both setup & hold violations are possible in the same path.
setup analysis will be done in the slow corner, where as hold is done in the fast corner.
Now, look at this way, the combo path consists of only HVT cells ( which usually gives more delay in slow corner, less delay in fast corner ). This is due to delay (...)
ASIC Design Methodologies and Tools (Digital) :: 08-14-2015 11:19 :: kumar_eee :: Replies: 8 :: Views: 2598
Suppose I am having a D flip flop.
Now what are the parameters those affects the setup and hold time of the same?
If I want to change it, how to change it?
ASIC Design Methodologies and Tools (Digital) :: 07-31-2015 13:13 :: aanudhonde :: Replies: 5 :: Views: 576
check this link
Fixing setup & hold Violations
ASIC Design Methodologies and Tools (Digital) :: 07-14-2015 01:48 :: hanif :: Replies: 1 :: Views: 662
I saw CPPR adjustment is added in the setup path and subtracted in the hold timing.
What is the Purpose of CPPR.
and hold time is calculated at the same edge of clock at two flipflops... so if a hold violation occurs then there is a possibility (...)
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 04-10-2015 14:52 :: kenambo :: Replies: 0 :: Views: 1410
Memory cells, FF's or any edge sensitive logic must have a setup and hold time must have data stable for this amount when the worst case clock skew edge occurs. This is a standard requirement for synchronous logic.
Otherwise for asynch logic, race co
ASIC Design Methodologies and Tools (Digital) :: 03-29-2015 18:39 :: SunnySkyguy :: Replies: 4 :: Views: 1270
What is the difference between Timing analysis done in Design Compiler , Prime time and ICC Compiler. Which tool is preferred ?
How do we fix setup & hold violations using Design Compiler ?
Post Synthesis (library.db and gatenetlist.v are given as I/P to (...)
ASIC Design Methodologies and Tools (Digital) :: 01-21-2015 05:24 :: praneethrajkanakam :: Replies: 3 :: Views: 2079
Probably a misunderstanding of SPI operation. SPI is designed to have setup and hold time of about 1/2 clock cycle by launching data at one clock edge and sampling it at the other edge.
In so far, a 10 MHz SPI interface doesn't require any particular precautions (...)
Analog Circuit Design :: 11-23-2014 11:16 :: FvM :: Replies: 10 :: Views: 1359