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22 Threads found on edaboard.com: Hold Time Slow
Hello all, I have 2 questions here Setup and hold violations in same path - yes / no ? Setup and hold violations on the same flop - yes / no ? I have know that setup and hold violations cannot come on same flop as it will lead to metastability and the exact data will not be captured or we will not get the exact value. If i am (...)
Because hold time check is on the same clock edge. Clock slow or fast won't affect the result.
Hi All, As for the SetUp and hold checks, should I run the PT tool twice each time for either SetUp Or hold check? If the tool is able to read slow and fast SDF and libs together, why not running it only once for all kind of the checks? Thanks!
Jeevan , can you discuss why exactly you need hold anaylsis before CTS...hold fixing is not in true sense an optimization process, its a degradation or relaxation step... since we have realistic clock skew, latency, and delay values POST CTS, thats why we do hold fixing after analyzing the final need and hold violations. (...)
We use slow libraries for setup time and fast libraries for hold time voilation check. Why it os so?
Sometimes we may have timing violations at typical corner, especially for hold time.
Hi! I have question on how voltage, process, and temperature will affect setup and hold time violation, can anyone explain to me? What's the worst case ? what's the best case? Thank you.
I'm trying to use a stepper motor for my first time. I have managed to get it spinning using a 16f84a. But it is getting quite hot, is that normal? And what is the correct way to apply hold torque?
he's right. slow/slow for setup. fast/fast for hold.
Hi ASIC_intl, When the clock signal transation time is too slow and the data signal transation time is too quick, the setup time will be negative. And the setup time + hold time >= 0. The total of setup time and hold can be view as the (...)
in the slow.lib(for example) u can find these two parameters: constrained_pin_transition and related_pin_transition what i want to know is how does tool get these two transition time?thank u remark : constrained_pin is D of a DFF related_pin is CK of a DFF
I think this should take your margin into account,maybe different margins for setup/hold,then the risk is different.
shahal, leeguoxian, Frequency of operation is not as important during scan shifting. Therefore, we can always slow down the freq and/or modify the duty cycle to remove a hold time problem with data lockup latches. If your skew is big, then you will need a lot of buffers or delay cells, which is undesirable for power/area etc.
For setup time you need clock buffer to change clock skew. For hold time you need delay buffer to slow the data.
When hold fail, the chip does not work in any frequency (even 1hz).
can any one tell what all libraries pks tool consists of ? is that timing lib for slow.lib & fast .lib those r for set up hold time of i right.../??? & LEF states only tech files......correct me if i am wrong??? wat all other components pks consists of?
As advice from synopsys, sign-off STA should be four times STA in two corner, slow corner and fast corner. You should run STA by primetime. Use bc-wc analysis mode. Set slow library, check setup time and hold time. Set fast library, check setup time and (...)
To make on chip variation minimum, you should use both stage match and metal match. For hold time check, you can use fast data and slow clock for back-annotated SDF.
The hold time don't affect the frequency. That is, if there is a hold time issue, you can't fix it by slow down the clock. So it's more diffcuity to improve the hold time issue. i think u are incorrect,hold time violations can be (...)
Setup time violations are corrected in two ways. First, extra buffers can be inserted to speed up slow signals. Second, if buffer insertion does not completely fix the setup violation, the placement can be re-optimized. hold-time violations are fixed by inserting delay elements into fast data paths. Excerpt (...)