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# Hspice Gate

92 Threads found on edaboard.com: Hspice Gate

## How to simulate MOSCAP or MOS varator by using macro model

Hi I am using hspice to simulate the cap value of MOSCAP or MOS varator. In the older processes, we can print this parameter "lx18(m1)" to get the gate capacitance. However, foundries provide the macro model for the recent processes. My question is How to simulate MOSCAP or MOS varator by using macro model. Thanks. CD

## calculating overall Cgs of MOSFET

Hey, you can get Cgs information from the Spectre or hspice simulation. Vgs is different due to the different bias condition.

## Power trace in Hspice

Hi all, I want to obtain a power trace from a circuit in hspice. I don't know how to do this. To be more specific about my problem, assume a circuit with a simple 2-input AND gate. While one input (say, input A) is fixed at logic 1, the other input (input B) oscillates between 0 and 1, and hence the output (say, C) oscillates as well. How can I ob

Hi there, I an designing 10-bit pipeline ADC in hspice. It works good with ideal switches. However, when I replace the switches with the ideal one, face the following error: **error** internal timestep too small in transient analysis Does any one knows about the reason? Please kindly let me know about the reason. Thanks

## [moved] Delay calculation of 2 input NAND gate by using hspice

I have written code in following format. While simulating my code it was not showing any errors. But in my .lis file it showing tpHLnand and tpHLnand values are failed. and delay is also failed. what does it mean??. Can you please help me. Iam new to hspice. Thanks.. .tran 0.1p 100u .probe v(V1) v(nandout1) .meas tran tpHLnand trig V

## How to build a simple logic gate by using VCVS in Hspice

Hi, Anyone knows how to build a or/and/nor gate with VCVS in hspice commond line( hspice code)? The syntax is : Multi-Input gates Exxx n+ n- gatetype(k) in1+ in1- ... ink+ ink- + x1,y1 ... x100,y100 But can anyone give me an example (...)

## i need example of finfet code in hspice

hi i want to write a code of finfet in hspice but i wanna find a correct model of finfet same as BSIM-CMG i write this code and i wanna replace model of this code instead of 45nm & 20nm finfet code ** PTM-MG 20nm hspice Model Card for HP NFET ** Nominal VDD=0.9V * This is sub 45nm FinFET prdictive model .options p

## How do you implement not gate in hspice using "NangateOpenCellLibrary"

hello i want to implement gate not in hspice using "NangateOpenCellLibrary_PDKv1_3_v2010_12". can you help me step by step how do it? thank you

## CMOS voltage swing problem

I modelled an XOR gate using hspice (Transistor level).Input voltage signal is 4V and Vdd of the circuit is 5V (threshold voltage= 1v). While giving input voltage 4v I got Maximum output voltage swing as 5v, So my problem is I cant cascade the output of this XOR gate(5v) with another XOR gate beacause it will turn off (...)

## HSPICE subcircuit design problem ?

I want to design below circuit in hspice , Technique used is GDI . 116902 The Code is given below. * Circuit. .OPTIONS LIST NODE POST .TRAN 200P 100N .PRINT TRAN V(IN) V(OUT) X1 IN11 IN21 OUT1 AND X2 IN11 IN22 OUT2 AND X3 IN12 IN21 OUT3 AND X4 OUT2 OUT3 OUT4 COUT HALF .subckt AND INA VCCA

## estimation of Soft Error Rate using Hspice

Hello everybody, I want to estimate Soft error rate of iscas85 circuits using hspice.I add current pulse to a random transistor's node of a gate in a specific time moment and observe a voltage drop at the output of this gate. Should i examine how voltage drop attenuates passing through the other gates of each circuit and (...)

## 3 gate oscillator output waveform is okay in TSpice but not in HSPICE

When I ran the code below in TSPICE, a 5V pulse waveform was generated. However when I ran it in hspice, a 2.5V dc straight line waveform is generated. Do I need to modify some code to generate a pulse waveform in hspice? Thank you! *3 gate OSC .PROTECT .LIB 'C:\Users\MM0355V.L' TT_5V .UNPROTECT .SUBCKT INV A OUT VDD VSS MN1 Ou

## doubt on hspice declaration of pwl for multiple gates at atime

Hi I am implementing the circuit which my friend is working doubt is in the below diagram attached,there are inputs from N number of inputs,how to delcare the input PWL waveform for each of them say n=64,should i declare 64 times for each of the gate or else any short cut we have ,plz help.

## hspice file handling operations

Whether we can call a .sp file inside another hspice file other than model parameters. If so how to do that.

## FinFET simulation in 16nm in HSPICE

Dear everyone I need to simulate an SRAM cell in hspice via FinFET technology. How do I perform this? It means, for example, in CMOS, we have Drain gate Source Bulk. Now, in FinFET, how is this instruction? Many Thanks

## [Moved to new thread]: how to measure aging effects on SRAM in HSPICE?

Thanks, how to measure aging effects on SRAM in hspice?

## Using Verilog/VHDL with HSPICE?

My problem is that I have an analog circuit (in the form of an hspice netlist) that monitors some parameters of my digital circuit (in my case the drop in the supply current caused by the computation of the digital circuit). I made a SPICE simulation with some simple digital circuits, but now I want to simulate more complex one. What do you think

## SPICE radio frequency amplifier design and optimization

Dear all. Recently I have started designing a radio frequency amplifier based on dual-gate MOSFET BF998. I have simulated it in hspice simulation software, designed input and output matching networks. Unfortunately, This is a four-parameter problem which is suitable to be solved by optimization technique. I need to optimize three inductors and one

## Using PTM model in hspice and measuring the leakage power of bulk cmos and finfet(DG)

Hi,everyone: Could you give me a hand to solve following questions? (1)I download the predictive technology model for 32nm finfet(double-gate) technologies from the website ( ) ,but I found one of the files , 32nm_finfet.pm, which described the double-gate used two parallel connection transistors, like this: [ATTACH=CONF

## Spice simulation of Gate Level Netlist

Hi Akash you can use hspice(synopsys tool) or Virtuoso UltraSim Simulator (cadence tool) for your analysis. these tools can convert netlist into spice also.