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33 Threads found on Hspice Leakage
Hi, I'm trying to measure the delay in hspice for an inverter by using .measure command. **Test inverter .TEMP 110 **Use high temperature to simulate worst case delay and leakage power .OPTION + ARTIST=2 + INGOLD=2 + MEASOUT=1 + PARHIER=LOCAL + PSF=2 + P
i have written a hspice code for d flipflop and i want to calculate the delay of the circuit i.e. high to low and low to high propagation delay but my code is running but not able to give the values of delay * dff.sp ***********dff*******************8888 * Parameters and models *------------------------------------------------
Hi, I have simulated a 6T conventional SRAM by hspice. Its value of leakage power is achieved negative one about -75nWatt. What's the problem? By the way, another issue adumbrating my results is peculiar current spike of pulse sources associated with BL and BLB as shown in attached Fig. Many thanks in advance 112536[/AT
Dear Scholars I'm gonna initiate my thesis through simulating an 6T SRAM cell and measuring its parameters such as leakage, SNM, Read delay, and etc. Unfortunately, that section dealing with read delay is obscure for me in the aspect of simulation in hspice. I would be most grateful if you could help me to measure read delay of SRAM. Many thanks
Dear researchers I am redesigning a conventional SRAM 6T. How to measure leakage current in SRAM by HSIPCE? I mean that I need required code to apply to hspice environment. Many Thanks
Hi,everyone: Could you give me a hand to solve following questions? (1)I download the predictive technology model for 32nm finfet(double-gate) technologies from the website ( ) ,but I found one of the files ,, which described the double-gate used two parallel connection transistors, like this: [ATTACH=CONF
99473 I got the above waveform. I need to get like below: 99474 It's switching leakage current. How do I do? Below is my code. __________________________________________________________ Vdd vdd gnd dc=1v * --- Source --- Vgate gate gnd 0 * --- 1 unit Inverter --- Mp1 drain gate vdd
hi all, i have a fsm. i want to have the leakage power in hspice. i dont know how to do that? tanx
hi all, i used the v2s command to convert a fsm to its spice model. now i have the spice model and i want to estimate its the leakage power! i do not know how to do this please help.( im using nangate 45nm) tanx
hi all, i used the v2s command to convert a fsm to its spice model. now i have the spice model and i want to estimate its the leakage power! i do not know how to do this please help.( im using nangate 45nm) tanx
Good Aftrnun to everyone:About hspice COMMAND For setup,hold,leakage power,Dynamic power. I added for my cell i.e., Delays , risetime and falltime cell is Negative edge Dff synchronous with active low set .Any one say hspice commandsIf Somebody give any suggestions it is very helpful to me...
Hello everyone I want to find gate leakage current in 45nm cmos model. I have found some sample for calculating leakage current but they are not work correctly. Here is my code: spice deck .inc '../' .inc '../' .inc 'AND2_X1.sp' vcc 1 0 1 v1 vs 0 1 v2 vd 0 0 X1 vs vs out 1 vd AND2_X1 c1 0 out 1p .tran 1ns
hi why in some calculate power in hspice input frequence (p=(v^2*c*f_/2))i use for nanad gate.but in nor gate and xor gate (p=(v^2*c)/2)) i dont use frequance in my calculation and result was i wrong?
i want to fimd leakage current in nmos and my hspice coding is... vdd 1 0 dc 1v m 1 2 0 0 nmos w=1u l=65n vgs 2 0 dc -.1v .include '/home/student1/65nm_bulk.txt' .tran 5n 200n .probe tran i1(m) i2(m) .option post probe .end but result is show zero my code correct..if not then tell me how we calculate leakage in nmos... plz rep
Add supply voltage source first. Set supply voltage for practical application. Add periodical signal for CK. If you are not sure about the application, just connect QB to D as 1/2 frequency divider. Here, QB is input of I6. And run hspice and probe the current of the supply voltage.
can someone help me ?i want to know how to use ISCAS 85,if I want to konw the leakage .for example use hspice .
.option post .include "F:\New folder\45nm\45nm low vth.l" *.include "F:\New folder\45nm\45nm high vth.l" vcc vcc GND DC 0.8v vss vss GND DC 0V * vck 1 0 pulse(0.0 0.8 0 0.01n 0.01n 0.49n 1n) M1 1 A vcc vcc penh M2 1 A vcc vcc penh M3 1 A vcc vcc penh M4 1 A 2 vss nenh M5 2 B 3 vss nenh M6 3 C vss vss nenh va A 0 0v vb B 0 0v
Hi, I have questions on how to simulate 65nm technology leakage current using hspice C-2009.03-SP1, and the model from foundary is BSIM4 V4.5 LEVEL54. As we know, subthreshold leakage, gate tunneling leakage and junction tunneling leakage are the three main parts in DSM technologies. In our job, we need (...)
hi~ there~ please help me~ T.T how to measure leakage current or leakage power using hspice? here is my .spice~ +++++++++++++++++++++++++++++++++++++++++++++++++ .include ../nd2.spice vdd vdd 0 1.8 vss vss 0 0 .param slew = 0.04n .param load = 0.01p vin1 a 0 pwl(0 0v 10n 0v '10n+slew' 0v 20n 0v) vin2 b 0 pwl(0 1.8v 10n (...)
Hi All, I am using hspice generated netlist for simulation and I am simulating leakage based circuits. I wanted to do fast simulation using nanosim as the VCO simulation takes a long time in hspice. I wanted to use different accuracy levels for the various blocks in the circuits, viz high accuracy for analog blocks and lower accuracy (...)