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Huge Violation

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5 Threads found on edaboard.com: Huge Violation
RTL needs to be synthesized to see timing violation. Synthesis team gives their feedback to RTL team if there are huge violations synthesis. RTL designer modify RTL for those particular paths.
1- is the design is timing clean before the postroute? a- if yes, it is also DRV clean, is there huge routing hot spot, which could have been not properly handle before? b- if no, fix the setup before routing.
How about hold slack/viol ? If you got 88000ns positive slack with 111ns cycle time, it must have a huge clock skew, pushing the capturing clock edge way ahead, and natually it's likely to have a hold violation. THe clock skew remains the same regardless of the cycle time, and capturing edge is always at the same location in time. It seems to m
hi, my 2 cents, * Is there any specific reason to have such a huge hold margin of around 400ps? if you reduce this then your problem would be simpler to solve or less buffers. * Do you checked whether clock tree information is there for the input port or modelled, usually the capturing register will have the clock tree values but the por
If the violation are few in mumbers. Try to do manual adjustment on the routing, If it is huge in number, try to find the reason why it is occuring, ex: try to place your Blocks and Std cell optimally or try to change the floorplan to have more routing area for the signals