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15 Threads found on edaboard.com: Ieee Bus
I do have following block diagram which I would like to connect with a bus that use a generic parameter (adc). The blockdiagram looks like this: 127009 The implementation for the file "block_name.vhd" is: LIBRARY ieee; USE ieee.std_logic_1164.all; -- Entity Declaration ENTITY block_name IS
can any one help me to calculate the installation and maintenance cost of ieee 33 bus system
the TDS2024 has optional interfaces for RS232 and GPIB (ieee 488 bus) if your oscilloscope has such an interface you such be able to connect to to a PC it would probably give you control of scope functions but I doubt if you could get a real time display check the manual
i am implementing sap-1 in vhdl.but i cannot make system bus and controller circuit. here is my code of controller.if possible fix the error.i will be very great full library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use work.all; entity (...)
Hi Does any one have the code for the Gauss-seidel method for the ieee 14 bus, in fortran, C and matlab. Thanks
I need to insert some user defined delay on a bidirectional bus in VHDL. Ho wcan I do this? I am using a delay inserting module as follows: library ieee; use ieee.Std_Logic_1164.all; entity WireDelay is generic (Delay_g : time); port (A : inout Std_Logic; B : inout Std_Logic ); end WireDelay; (...)
hi, i need verilog code urgently for ieee 786 microcontroller bus protocol if any one is having please reply me immediately
The Dallas Semiconductor DS80C400 is an 8051 based High-Speed Micro with 4 DPTRs, ROMless, WDT, 3 Serial Ports, CAN Controller, 4 Timers/Counters, ieee 802.3 Ethernet Interface with TCP/IP in ROM, 1-Wire Net Controller, 64 I/O Lines + Address/Data bus, 16 Interrupts/3 Priority Levels, 256 Bytes On-chip RAM, 9K Bytes On-chip SRAM, 16/32-bit Math Cop
Hello! Anybody out here who is using Anritsu Wiltron 54xxA series scalar network analyzer? Could be 5407A, 5409A, 5411A, 5417A or something similar. There had once been a PC program that has done TDR measurement via the ieee 488 / GPIB bus. The program was locked with a dongle. I was able to find a dongle, but not the program itself. Is here
Is it possible create a Bidirectional bus without FlipFlop in VHDL ? LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY bidir IS PORT( bidir : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0); oe, clk : IN STD_LOGIC; inp : IN STD_LOGIC_VECTOR (7 DOWNTO 0); outp : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
Hi I have just been reading the ieee spec and they talk about active true, active false, passive true and passive false. Can anyone explain these terms in relation to the signals on the GPIB bus Thanks
I can't find the specification of the reduced MII (RMII). I search by RMII Consortium, ieee, RMII bus, but nothing. can anyone give me that specification or the link. thanks for advanced
I need to connect several boards by means of a backplane. I have a limit in the number of pins and was thinking in some serial bus as 1394, but I have a lot of doubts. How many lines do I need? 2 differential pairs? should I implement a switch?
I did a simulation of a sample in my Max+Plus II 10.23 the sample is: bidir.vhd (Tri-state bus implementation) --************************ LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY bidir IS PORT( bidir : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0);
you can get ieee 1014 from it's website