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52 Threads found on edaboard.com: Incisive
Hi, I want to do accurate power estimation using cadence tools on a simple design with 8 flipflops and a fulladder involved. the only cadence tools avaialbe with me is, incisive entreprsise and genus. i learned to generate power report, but this time i want to keep invovle forward saif, backward saif files (came to know from internet) for
Xilinx ISE is old and so is ISIM, you should refrain from using them. Better would be to use Vivado and its integrated Vivado Simulator. While questa, incisive are much better but Xilinx is giving Vivado for free (free version). You still didn't mention if you have funds at you disposal. If you have go for VCS Synopsys. Vivado Simulator supports
Hi. Does anyone know what is difference between base and hotfix in cadence incisive tool? Can we use just hotfix type not base?
hi, I am new user of cadence incisive unified simulator. I want to run a mixed signal simulation. I am able to run a mixed signal simulation of a design consisting of a verilog module and an analog schematic module, when using cells only from analogLib in the schematic. The problem is when I use the cell from the foundry library there are errors in
Hi All, I am looking for specific commands in the ncsim tool where the user can stop the simulation when it is on going - check the result and start it from the point it had ended the last simulation on. Will breakpoint work in this tool. Regards Limitless
Hi All, Could someone share incisive/NCsim Training Materials from Cadence? Thank you!
Can you guide me how to run ovm and uvm in Cadence incisive and Synopsys VCS.?
i Ma M.Tech Student.. I would like to do project in Cadence incisive.. May i know which topic is best to complete within 6 months..?
Hello Everyone i am getting a warning because of $shm_probe failed. ncsim: *W,SHMPFL: $shm_probe failed. Can anyone tell me how to remove that warning. Thanks And Regards Mukesh Goyal
The short answer is yes you can. Though you will require a mixed language simulator that has full SV support, like Questa, Riviera, incisive, etc. Most of those tools are $20K-$30K tools. I've only run across one free SV tutorial for someone without a company email address. It was posted by the creator of the tutorial.
ModelSim / VCS / incisive all support UPF, to varying extents, providing you have the right license, for power-aware simulation. They don't model voltages like an analog simulator, but you can see why power domain signals are in.
Hi, I'm running post simulation with incisive tool, but always be headache to deal with those glitches for pads. The pad always has big delay while the signals period is smaller than it. I have tried to adjust pulse_r/e parameters to let signals go through pad and filter those small glitches, but this step is painful and frustrated me always. Some
All tools like cadence incisive, synopsys vcs, mentor graphics modelsim support transistor (switch level primitives) as defined in verilog standard. See those primitives here
Modelsim is sort of an industry defacto standard. Xilinx ISIM is for Xilinx parts only and is still not as good as Modelsim incisive is a Linux/Unix based simulator from Cadance Aldec is a another PC based simulator that competes directly with Modelsim on features. VCS is synopsys' simulator which is very fast and is Unix based (funny how Googl
Hi everyone, please help me with the next problem: I'm designing a digital IC based on FPGA-verified source code using Cadence tools: Encounter for P&R and optimization and incisive simulator (NCSim may be the second name) for checking the resulting waveforms. After P&R, in post-route stage, I optimized design using the next commands: optDe
hello there i have a problem while i try to run ifv i source the ifv_setup which located at: ifv/bin folder and there what it says: ifv_setup : (c) Copyright 1995-2009 Cadence Design Systems, Inc. bash: /home/edatools/INCISIV-10.20.026/tools/ifv/bin/ifv_setup: line 11: syntax error near unexpected token ``/bin/uname`' bash: /home/edatools/I
Hi All, I'm using Cadence's incisive tool to perfom simulation and code-coverage analysis. My desgin has 2 process FSM modelling style (means combinational and sequential logic defined in two separate process). Problem is not able to do FSM extraction getting below message from log file : Extracting FSMs for coverage:
incisive belong to the simulator tool!
AMS is more accurate while incisive simulator not so good for mix-signal simulation !
Hi, when i run the simulation i am getting the following error VPI TUINVLD can anyone please if you know the meaning explain the error i am not getting any info on the same thanks kiran