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17 Threads found on Inl Pipeline
Hello Everyone, I am designing 12 bit pipelined ADC. I am facing problem to get the accurate gain of 2 from the designed MDAC when I use the capacitors from technology library. When I replace the CI and CF capacitors with the ideal caps I get accurate 2 gain when I check the residual output of each stage, also inl of +-0.5LSB and also no PVT vari
I need Matlab code of pipeline adc to evaluate inl error for some situations such as MDAC gain = 1.9 , 1.98 , 2 , 2.02 , 2.1 (8bit pipeline ADC and 14bit pipeline ADC - only first stage) Thank you very much.
Hi, I am going to build the simulink models of a pipeline ADC, including SHA, each stage of pipeline ADC,clock generation, digital correction. The non-ideal of switched-capacitor opamp should be included. Eventually I can get the plots of inl, DNL, SFDR, SNDR, and ENOB in the Matlab. Is there any examples I can follow? Or where to get more (...)
Hi, I am building a 10 bit pipeline ADC using Simulink.I have got the output in steps of 0-1023 at the output.I have used a ramp input as the input signal. Is there a way to perform calculations for SNR,ENOB,SINAD,DNL and inl(theoretical and practical as in using Simulink) for the block in Simulink using the ramp signal. And how do I know whet
Diff nonlinearity is the difference beetwen widths of ideal ADC quant and real. nonmonolicity appears when DNL > 1LSB i.e. one of real acd quants became wider then 2 ideal quants and thus "eat" the neibghour quant. in the situation with ideal ADC but when one quant is just missing in the point you have missing code, value of DNL there is should
the second harmonic, and the even harmonics, will go down in a differential system (especially in simulation). SFDR is important as it is a measure of linearity (somewhat correlated to the inl). Many papers do show DNL/inl therefore SFDR is not needed.
for a pipelined adc, the performance of it (SNR\SNDR\inl\DNL\THD etc)will decrease with the increasing of input sine frequency; then what's the reason? for a 10bit 15M pipelined adc(just for circuit simulation, not for the chip test), its ENOB=9.8 at 300k input sine frequency, while when input sine frequency increases to 7.5M or so, its (...)
1) DNL is affected due to comparator offsets and due to gain error of the opamps in the mdac sections. the inl is just a cumulative sum of the DNL. the SNR, THD are frequency content parameters. the finite gain and bandwidth of the ota in the mdacs, the bottom plate capacitances, the error in capacitor values and many more will have a toll on t
I am now simulating a pipeline ADC in cadence, I want to get inl/DNL from some programs run on matlab, how can I get the simulation data from cadence spectre,and to use it in matlab?
You can include an ideal DAC to check the difference in deriving inl/DNL
HI all I am testing a 11-bit ADC inl and DNL. I have read the maxim histogram test app note. But I have some questions about the test setup. 1) For 11-bit and 27MHz sample clock, how to add the input sinwave signal. what the frequency of the sinewave signal. How can i guantee the sampling chance for every code is equat
a document can be obtained from foundry when a project is begun. DNL and inl of ADC can be estimated. Architecture of ADC is sure.
I finished a 10bit--20Mhz pipeline ADC,but i don't know how to measure the DNL and inl .I want to use Verylog-A.Can anyone give me some ideas in details.For example one step,two step.....waht's "vtran=..."mean?Thanks!
u can export ur adc output to matlab workspace, and then use ur inl.dnl mfile to analysize it. u r correct.
im not quite sure abt all this testbed(cct) for testing pipeline ADC performance such inl,DNL,SNDR & FFT using Cadence. Do anyone have some testbench cct for these performance metrics ? i knw it need to be done in transient.. but how about testbed signals ???
Would like to ask if anyone have successfully obtained the inl and DNL using the histogram method by maxim? I'm still unsure how to setup the logic analyzer to obtained the data needed.
Hi, Could anyone help me on what is the latest spec (current, inl, DNL, speed) for the pipeline ADC. Thanks in advance