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Input Buffer Synthesis

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4 Threads found on edaboard.com: Input Buffer Synthesis
i believe what the tool here is doing is correct. Basically synthesis is not only supposed to map the RTL to technology gates but perform optimization as well. Further in your case say 2 back to back inverters would give the same logic as output which was at the input stage thus a buffer. The same is what 6 inverters i.e.3 pairs of inverters (...)
IOB = input/output buffer -- the physical pins on the part. This issue occurs because the tools will default to automatic IOB insertion. There should be synthesis options to disable automatic IO insertion for the purposes of making an IP core.
In my design,some signals like this: module test ( a,b,...... ) input a; output b; ...... assign a = b; endmodule After synthesis,this statement didnot substitute by inserting a buffer!But this statement cant be recognized by Encounter. How to eliminate this "assign"?
I am synthezing my design for Xilinx device. I find that one of my input signal which is not a clock is being through the global clk buffer. How can I force the synthesis tool to not use the clk buffer for this input.