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50 Threads found on edaboard.com: **Integrator Noise**

Hello naderi,
In a delta sigma modulator, it is well-known that only DAC and the first **integrator** can contribute to the output **noise**. It can also be tested by behavioral simulators such as Matlab and verilog-A.
I found that transient **noise** analysis is not match with **noise** analysis. An experienced designer told me that he

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 06-11-2011 04:58 :: Manjunatha_hv :: Replies: **9** :: Views: **6387**

Hello,
Hi,
I need a favor from you. I am designing SC **integrator** kind of similar circuit but, instead of cap using big resistor. I would like to know how to analysis the circuit in terms of **noise** Analysis, apart from transient simulation, anything simulation like mentioned SwitCap simulator.
Please, guide me on

Analog Circuit Design :: 06-11-2011 04:53 :: Manjunatha_hv :: Replies: **3** :: Views: **1784**

I am really facing problem while doing **noise** simulation of Continuous TIme **integrator**.
I am using Spectre simulatior
Which is correct method to do **noise** simulation ?
**noise** in ADE or
PSS, PAC and P**noise**They give same result as far as small signal operation.
You post completely same question in the (...)

Analog Circuit Design :: 05-18-2011 14:23 :: pancho_hideboo :: Replies: **1** :: Views: **1311**

Sampled Mode exists in PAC and PXF of Cadence Spectre.
This mode is similar to "timedomain" mode in P**noise** Analysis of Cadence Spectre.
The Designer's Guide Community Forum - switched capacitor **integrator** **noise** simulation results
However I can't get reasonable results for

RF, Microwave, Antennas and Optics :: 05-16-2011 15:55 :: pancho_hideboo :: Replies: **0** :: Views: **2191**

Hello all,
What can limit the input signal level for a delta sigma modulator?
I used an example given in the delta-sigma toolbox from Matlab and optimized a 3rd-order NTF for:
-Continuous-time with RZ DAC
-all poles at DC.
-out-of-band **noise** Hinf=1.7
-BW = 20kHz
-OSR = 128
-cascaded-**integrator**-feedback (CIFB) structure.
(fs=5.12MHz, U

Analog Circuit Design :: 03-12-2011 00:22 :: naderi :: Replies: **0** :: Views: **1050**

why **integrator** op-amps are overused than differentiator op-amp in practical circuits or in solving problems?

Analog Circuit Design :: 02-13-2011 11:55 :: debaleena bhowmik :: Replies: **2** :: Views: **823**

I designed a 2-1 sigma-delta modulator and found fft issue I don't understand. My sim has 2 steps:
1) run "tran" analysis in spectre (select "Transient **noise**" option)
2) read data from modulator output to matlab and do fft in matlab
I used 2 different sampling capacitors (1pF, 4pF) for the first **integrator** and other parameter (fclk, fsample, N

Analog Circuit Design :: 11-10-2010 22:52 :: xuedashun :: Replies: **5** :: Views: **3578**

Yes.
The real cut-off frequency of this **integrator** is ARC, as you can derive by simple transfer function analysis.
Of course, the price you pay is increase in **noise** and power consumption.

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 09-15-2010 11:35 :: kgl_13gr :: Replies: **4** :: Views: **1014**

Hi,
I try to match model of first order sigma delta to spectre simulation results, but they disagree!
First figure attached is first order sigma-delta model (comparator shown as a summing node and **noise** source N(s)). Can solve to get:
Y = N/(1+H) + H*X/(1+H) where H=K/s
So if K/s >> 1, then:
Y ~ sN/K + X
This says to me that to

Analog Circuit Design :: 07-16-2010 22:18 :: ansu_s :: Replies: **1** :: Views: **1304**

I figured out that the NTF is indeed quite flat in that band. It is a 3rd order modulator with cascaded **integrator** and feed-forward

Digital Signal Processing :: 01-10-2010 04:22 :: neoflash :: Replies: **3** :: Views: **2668**

Hi,
Can any one tell how to determine requirements of of the amplifier of single stage Sigma Delta modulator.
It is clear that sampling frequency and maximum input range will determine GBW and SR of amplifier. But how to determine required DC gain, offset **noise**.
If we have as task to make ADC with certain resolution let's for example 16 b

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 07-23-2009 10:02 :: tyanata :: Replies: **1** :: Views: **1391**

Hi,
Can any one help in doing in **noise** simulation of SC **integrator** - part of a incremental sigma-delta ADC?
Any good reference or simulation type details will help a lot.
Thanks
Sanku

Analog Circuit Design :: 06-26-2009 08:18 :: sankudey :: Replies: **1** :: Views: **1717**

the output would be zero Not exactly. It's still **noise**, with 1/f spectral density, like semiconductor flicker **noise**. And strictly spoken, an **integrator**
has possibly a DC offset.

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 05-05-2009 06:32 :: FvM :: Replies: **2** :: Views: **1876**

the **noise** in sigma-delta modulator loop is shapped by preceding **integrator**s, for example the **noise** on the output of the first **integrator** is first-order shapped and the **noise** on the output of the second **integrator** sencond-order shapped. but the **noise** to input of sigma-delta (...)

Analog Circuit Design :: 06-18-2008 13:54 :: jiangxb :: Replies: **1** :: Views: **929**

Hi all, I come across this paper and would like to try it out on Simulink.
With regards to the block diagram, should I use the Discrete-Time **integrator** from Simulink to represent Discrete **integrator** in the blo

Analog Circuit Design :: 03-24-2008 12:33 :: taik :: Replies: **1** :: Views: **2156**

Hi,
I've encountered some problems in designing a 2nd order SDM.
the **integrator** outputs looks fine,
however **noise** shaping did not come out (as Attachment file)
can someone please tell what cause this happen?
thx

Analog Circuit Design :: 12-27-2007 07:23 :: shaper :: Replies: **2** :: Views: **1019**

to pfd001:
How to use **integrator** command?
In the analog design enviornment, you can find the calculator in the tools. In the calculator, you can use the integrate

Analog Circuit Design :: 09-18-2007 03:28 :: pfd001 :: Replies: **4** :: Views: **1690**

Depending on how your **integrator** is build up! I suggest it is built with an opamp. Then simple short with a switch between the cap instead of the output.

Analog Circuit Design :: 05-10-2007 15:29 :: rfsystem :: Replies: **7** :: Views: **4680**

Hi, all
I noticed for some SD ADC designs, ppl use CDS to decrease **integrator** leakage and flicker **noise**. For those of designs that circuit **noise**s are the dominant **noise** sources (i.e. quantization **noise** is not so obvious), how can I model flicker **noise** and white **noise** (...)

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 03-05-2007 21:36 :: TiwstedNeurons :: Replies: **5** :: Views: **3925**

Your problem is with reference source, that you use to shift the output DC level of triangle wave.
In histeresys block - switching occurs between two states, in middle is DC level
In **integrator** block - output integrates the **noise** of reference source (only elimine **noise** with zero mean)
Improve it.
Try a large capacitor to (...)

Analog Circuit Design :: 05-27-2006 12:46 :: teteamigo :: Replies: **1** :: Views: **2102**

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