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50 Threads found on edaboard.com: **Integrator Noise**

Why in RC **integrator** circuits , Caps are connected sometimes to supply voltage instead of ground ?

Analog Circuit Design :: 08-24-2016 15:48 :: Ltarek :: Replies: **5** :: Views: **385**

Thanks. One issue is that the output of the **integrator** is vdd or 0, since there is no dc feedback to control it, which gives a wrong simulation data.

Analog Circuit Design :: 05-27-2016 19:41 :: shanmei :: Replies: **7** :: Views: **1434**

Hi,
The signal and **noise** transfer function of a continuous time first-order delta sigma modulator using an simple active RC **integrator** both have a pole at 1/RC. The transfer functions are attached.115966
I was wondering, ideally, why can't we make RC very small, so the quantization **noise** is lower in the band of interest?

Analog Circuit Design :: 03-26-2015 23:57 :: raymond28j :: Replies: **0** :: Views: **484**

caps are used to act a a temporary or transient current shunt to **noise** voltage, the current is an **integrator** of voltage, also a DC block or RF coupler or an impedance vs f filter for bandwidth control.
There are millions of caps, with dozens of attributes, that define them uniquely.
pick 1 and ask for details with example schematic if that he

Elementary Electronic Questions :: 10-16-2014 19:34 :: SunnySkyguy :: Replies: **5** :: Views: **593**

Hi everyone,
Can someone suggest some papers or books or insight into the calculations for integrated vs. non-**integrator** **noise** components of a CTIA? I can't seem to find much of anything online...
Thanks in advance!

Analog Circuit Design :: 09-06-2014 00:27 :: koolposter :: Replies: **2** :: Views: **801**

103527Hi All,
I am studying the working of Delta Sigma(DS) and Incremental Delta Sigma ADCs. I am trying to implement those in Simulink. For DS I am getting proper output with **noise** shaping and good SNR. But when I am using the same structure for IDS with the reset connected to **integrator**, I am getting third and fifth harmonics

Analog Circuit Design :: 03-24-2014 07:16 :: karthikchanda :: Replies: **0** :: Views: **1606**

Hi all, I'm working on an optical sensor and am looking to increase my SNR. I've constructed a circuit to cancel out LED emitter **noise** with feedback control. PDref monitors just the emitter, while PDsig carries the sensor signal + emitter **noise**. Feedback consists of **integrator** -> JFET VCR -> current divider. Please see attached circuit. LT (...)

Analog Circuit Design :: 02-25-2014 23:38 :: RitchRock :: Replies: **0** :: Views: **430**

Hi, guy,
I need to design a large off-chip capacitor as the feedback capacitor of a on-chip current **integrator** for a large input current (over 10uA). However, I also need to use the same **integrator** to detection low level current (1pA). I know the input node Iin is very sensitive to **noise**. However, pad connection to (...)

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 12-12-2013 22:57 :: hyleeinhit :: Replies: **0** :: Views: **794**

Hi, I am doing a 3rd-order 2-bit CIFF DSM, I used Scherier's delta-sigma ToolBox to do the system design, ideally i can get 130dB SQNR with OSR=128. but i found the b1 and c1 coefficients are small so that the capacitors for the 1st stage **integrator** are very large when doing thermal **noise** budgeting. for this reason i increased the OSR to 256, this

Analog Circuit Design :: 12-01-2013 21:31 :: prcken :: Replies: **1** :: Views: **1018**

CIC uses modular arithmetic, overflow is by design. All CIC stages must have the minimal bitwidths according to CIC theory, then the output will be correct despite of **integrator** overflow.

Digital Signal Processing :: 07-29-2013 07:58 :: FvM :: Replies: **22** :: Views: **3376**

Well the above one is the basic block diagram of a first order sigma delta ADC. Now I am trying to implement that in hardware. Here's the image that I saw regarding the implementation in hardware. I have few doubts h

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 04-16-2013 04:24 :: iVenky :: Replies: **6** :: Views: **674**

Hi Jack,
A sigma delta modulator consists of one feedback loop around an **integrator** and a quantizer. This **integrator** (since you have 1/S therefore continuous) producing a low pass filtering of the input signal and a high pass filtering of the quantization **noise** which is injected at the quantizer, hense **noise** shaping the (...)

Digital communication :: 04-02-2013 12:49 :: jgk2004 :: Replies: **2** :: Views: **2481**

Hi All,
I am working on a **noise** dosimeter design. The hard part is that I can only use analog circuit...
I got stuck in the time **integrator** part. My circuit went through amplifier, A-weighting filter, RMS, exponet, and threshold all using analog.
So, I can take out all the signal below 90db.
Now I don't know how to build (a **noise** (...)

Analog Circuit Design :: 03-01-2013 17:53 :: kxl359 :: Replies: **7** :: Views: **1019**

Hi Everyone. I am implementing a Kalman filter for an accelerometer. As you know,the accelerometer can be modeled as a Random Walk process and the output of a random walk process is assumed to be coming out of an **integrator** driven by white **noise**. This is described in "Random signals and applied kalman filtering, Brown,Hwang" chapter 2&5. The book

Digital Signal Processing :: 09-23-2012 23:35 :: sharpedge3 :: Replies: **0** :: Views: **1195**

Analog Circuit Design :: 08-03-2012 14:34 :: errakeshpillai :: Replies: **4** :: Views: **2729**

75140
Inserted picture is the lossy-**integrator** in my circuit. To precisely run Simulink, I would like to calculate input referred **noise** for this lossy **integrator**, but I just don't know how to calculate.
Can anyone help me to calculate the input referred **noise** please?

Analog Circuit Design :: 05-30-2012 18:35 :: lawfulgm :: Replies: **6** :: Views: **1264**

I found a good article in 'analog dialog' from 1967 discussing the various errors and design issues with a Operational Amplifier **integrator** circuit.
But what about the Digital **integrator**. What would be the errors involved with a Forward Euler vs. Runge-Kutta etc..
---------- Post added at 10:22 ---------- Previous post

Elementary Electronic Questions :: 02-28-2012 15:22 :: digi001 :: Replies: **9** :: Views: **2080**

designing a Sigma delta 2nd order...CIFF architecture....
in literatures they hav suggested to use more linear and low **noise** first **integrator** for better they said first **integrator** is a power hungry one...
bt where the difference in design of low **noise** cum low power OTA and other OTAs lies... both (...)

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 09-14-2011 06:59 :: satyanitt :: Replies: **1** :: Views: **879**

HI ALL
i hesitated if this issue belong to this section but i will be very happy if some one of u will help me
i need to create sigma delta modulator for some application.
there is any section in the modulator that named **noise** shaping - it means that after oversampling signal we make **integrator** loops to the quantization **noise** and move (...)

Analog Circuit Design :: 08-27-2011 20:13 :: itmr :: Replies: **0** :: Views: **591**

An option is to use a type-2 PLL (one **integrator** in the loop filter). The output of the VCO is inquadrature with the input over the whole lock range.
Possible design issues to consider: acquisition time, tracking if the frequency changes quickly, phase **noise**, wide-range VCO.
The last one can be solved with a frequency conversion, i.e., insead of

RF, Microwave, Antennas and Optics :: 06-23-2011 01:58 :: zorro :: Replies: **20** :: Views: **2213**

Hello naderi,
In a delta sigma modulator, it is well-known that only DAC and the first **integrator** can contribute to the output **noise**. It can also be tested by behavioral simulators such as Matlab and verilog-A.
I found that transient **noise** analysis is not match with **noise** analysis. An experienced designer told me that he

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 06-11-2011 04:58 :: Manjunatha_hv :: Replies: **9** :: Views: **5340**

Hello,
Hi,
I need a favor from you. I am designing SC **integrator** kind of similar circuit but, instead of cap using big resistor. I would like to know how to analysis the circuit in terms of **noise** Analysis, apart from transient simulation, anything simulation like mentioned SwitCap simulator.
Please, guide me on

Analog Circuit Design :: 06-11-2011 04:53 :: Manjunatha_hv :: Replies: **3** :: Views: **1560**

I am really facing problem while doing **noise** simulation of Continuous TIme **integrator**.
I am using Spectre simulatior
Which is correct method to do **noise** simulation ?
**noise** in ADE or
PSS, PAC and P**noise**They give same result as far as small signal operation.
You post completely same question in the (...)

Analog Circuit Design :: 05-18-2011 14:23 :: pancho_hideboo :: Replies: **1** :: Views: **1084**

Sampled Mode exists in PAC and PXF of Cadence Spectre.
This mode is similar to "timedomain" mode in P**noise** Analysis of Cadence Spectre.
The Designer's Guide Community Forum - switched capacitor **integrator** **noise** simulation results
However I can't get reasonable results for

RF, Microwave, Antennas and Optics :: 05-16-2011 15:55 :: pancho_hideboo :: Replies: **0** :: Views: **1717**

Hello all,
What can limit the input signal level for a delta sigma modulator?
I used an example given in the delta-sigma toolbox from Matlab and optimized a 3rd-order NTF for:
-Continuous-time with RZ DAC
-all poles at DC.
-out-of-band **noise** Hinf=1.7
-BW = 20kHz
-OSR = 128
-cascaded-**integrator**-feedback (CIFB) structure.
(fs=5.12MHz, U

Analog Circuit Design :: 03-12-2011 00:22 :: naderi :: Replies: **0** :: Views: **965**

An op-amp is just that, an op-amp. In the real world reducing the upper frequency gain by turning the circuit into an **integrator** reduces the wideband **noise** at the output. A differentiator would increase the **noise** at the output and its function is avoided as far as possible.
Frank

Analog Circuit Design :: 02-13-2011 15:27 :: chuckey :: Replies: **2** :: Views: **723**

I designed a 2-1 sigma-delta modulator and found fft issue I don't understand. My sim has 2 steps:
1) run "tran" analysis in spectre (select "Transient **noise**" option)
2) read data from modulator output to matlab and do fft in matlab
I used 2 different sampling capacitors (1pF, 4pF) for the first **integrator** and other parameter (fclk, fsample, N

Analog Circuit Design :: 11-10-2010 22:52 :: xuedashun :: Replies: **5** :: Views: **2998**

Yes.
The real cut-off frequency of this **integrator** is ARC, as you can derive by simple transfer function analysis.
Of course, the price you pay is increase in **noise** and power consumption.

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 09-15-2010 11:35 :: kgl_13gr :: Replies: **4** :: Views: **823**

Hi,
I try to match model of first order sigma delta to spectre simulation results, but they disagree!
First figure attached is first order sigma-delta model (comparator shown as a summing node and **noise** source N(s)). Can solve to get:
Y = N/(1+H) + H*X/(1+H) where H=K/s
So if K/s >> 1, then:
Y ~ sN/K + X
This says to me that to

Analog Circuit Design :: 07-16-2010 22:18 :: ansu_s :: Replies: **1** :: Views: **1158**

I figured out that the NTF is indeed quite flat in that band. It is a 3rd order modulator with cascaded **integrator** and feed-forward

Digital Signal Processing :: 01-10-2010 04:22 :: neoflash :: Replies: **3** :: Views: **2482**

Hi,
Can any one tell how to determine requirements of of the amplifier of single stage Sigma Delta modulator.
It is clear that sampling frequency and maximum input range will determine GBW and SR of amplifier. But how to determine required DC gain, offset **noise**.
If we have as task to make ADC with certain resolution let's for example 16 b

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 07-23-2009 10:02 :: tyanata :: Replies: **1** :: Views: **1292**

Hi,
Can any one help in doing in **noise** simulation of SC **integrator** - part of a incremental sigma-delta ADC?
Any good reference or simulation type details will help a lot.
Thanks
Sanku

Analog Circuit Design :: 06-26-2009 08:18 :: sankudey :: Replies: **1** :: Views: **1532**

the output would be zero Not exactly. It's still **noise**, with 1/f spectral density, like semiconductor flicker **noise**. And strictly spoken, an **integrator**
has possibly a DC offset.

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 05-05-2009 06:32 :: FvM :: Replies: **2** :: Views: **1715**

the **noise** in sigma-delta modulator loop is shapped by preceding **integrator**s, for example the **noise** on the output of the first **integrator** is first-order shapped and the **noise** on the output of the second **integrator** sencond-order shapped. but the **noise** to input of sigma-delta (...)

Analog Circuit Design :: 06-18-2008 13:54 :: jiangxb :: Replies: **1** :: Views: **818**

Hi all, I come across this paper and would like to try it out on Simulink.
With regards to the block diagram, should I use the Discrete-Time **integrator** from Simulink to represent Discrete **integrator** in the blo

Analog Circuit Design :: 03-24-2008 12:33 :: taik :: Replies: **1** :: Views: **2027**

Hi,
I've encountered some problems in designing a 2nd order SDM.
the **integrator** outputs looks fine,
however **noise** shaping did not come out (as Attachment file)
can someone please tell what cause this happen?
thx

Analog Circuit Design :: 12-27-2007 07:23 :: shaper :: Replies: **2** :: Views: **892**

to pfd001:
How to use **integrator** command?
In the analog design enviornment, you can find the calculator in the tools. In the calculator, you can use the integrate

Analog Circuit Design :: 09-18-2007 03:28 :: pfd001 :: Replies: **4** :: Views: **1484**

Depending on how your **integrator** is build up! I suggest it is built with an opamp. Then simple short with a switch between the cap instead of the output.

Analog Circuit Design :: 05-10-2007 15:29 :: rfsystem :: Replies: **7** :: Views: **4277**

Hi, all
I noticed for some SD ADC designs, ppl use CDS to decrease **integrator** leakage and flicker **noise**. For those of designs that circuit **noise**s are the dominant **noise** sources (i.e. quantization **noise** is not so obvious), how can I model flicker **noise** and white **noise** (...)

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 03-05-2007 21:36 :: TiwstedNeurons :: Replies: **5** :: Views: **3629**

Your problem is with reference source, that you use to shift the output DC level of triangle wave.
In histeresys block - switching occurs between two states, in middle is DC level
In **integrator** block - output integrates the **noise** of reference source (only elimine **noise** with zero mean)
Improve it.
Try a large capacitor to (...)

Analog Circuit Design :: 05-27-2006 12:46 :: teteamigo :: Replies: **1** :: Views: **1973**

Hi, I have a stupid question about **integrator** **noise**..
Say an OTA has an input-referred **noise** Vn at it's positive input, and be connected into **integrator**, the transfer function (1/SRC) has infinite gain at DC, ideally.
So what would input-referred **noise** Vn be at OTA's output?
If I give input a (...)

Analog Circuit Design :: 04-28-2006 09:56 :: intuition :: Replies: **0** :: Views: **1263**

It is very difficult to say in a simple paragraph.
However, the key is the signal is almost untoched and **noise** is shaped by inserting **integrator** in front of comparator (Assumed that LP)

Elementary Electronic Questions :: 03-22-2006 23:25 :: ee484 :: Replies: **6** :: Views: **1649**

My question is how to extract the nonlinearity of a Gm-C **integrator**, i.e. THD (total Harmonic Distortion). SNR (Signal-to-**noise** Ratio) and SDR (Signal-to-Distortion ratio)?
As my knowledge, these perforamnces are from the FFT of a signal. Does it need a tranisent simulation???
In some literatures, the performances 1dB compression and IP3 can

Analog Circuit Design :: 03-03-2006 13:57 :: zoujunjx :: Replies: **0** :: Views: **831**

My question is how to extract the nonlinearity of a Gm-C **integrator**, i.e. THD (total Harmonic Distortion). SNR (Signal-to-**noise** Ratio) and SDR (Signal-to-Distortion ratio)?
As my knowledge, these perforamnces are from the FFT of a signal. Does it need a tranisent simulation???
In some literatures, the performances 1dB compression and IP3 c

Elementary Electronic Questions :: 03-03-2006 10:21 :: zoujunjx :: Replies: **0** :: Views: **1108**

hi guys,
I've been working on a sc **integrator** for a 16bit sigma-delta ADC.
while when i doing the bootstrap switches, the charge injection **noise**
and clock feedthrough give a lot of **noise**, even the charge injection can be
common mode rejected, there is still body effects (nonlinear) and clock feedthrough.
does anyone who did this (...)

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 11-28-2005 02:22 :: extraord :: Replies: **3** :: Views: **1468**

The characteristic parameters of op amp is relative to the loading and feedback factors of **integrator**.
In the meanwhile, the settling accuracy and **noise** requriement are the factor to determine the op amp.
I think the design of op is the core design for SCF.

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 07-26-2005 12:55 :: jiangwp :: Replies: **9** :: Views: **1575**

why not reduce ur total capacitance ?
why did u choose 9.6pF for ur **integrator** ? for **noise** issue, or matching issue?
by the way, what do u mean "5-bit coarse quantization", I have not heard about that term from books, is it a new technique ?

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 05-21-2005 13:03 :: Btrend :: Replies: **8** :: Views: **1748**

In contrast to sigma-delta modulators, delta modulators have their **integrator**(s) in the feedback path and not in it forward path ( input - **integrator**s - adc) . Therefore, no **noise**-shaping is done. Hence, it isn't usefull for oversampling converters.

Analog Circuit Design :: 08-24-2004 08:47 :: eda4you :: Replies: **4** :: Views: **2643**

the 4Kohm resistor has 2 reasons:
1. it's the reason described by petarpav.
2. if you use internal ref, the 4Kohm resistor and external cap (common 100nF), make the **noise** rejection of internal refference. (work as RC **integrator**)

Analog Circuit Design :: 07-26-2004 16:48 :: aNdreiBuuu :: Replies: **4** :: Views: **1458**

just as title said.I want to make a **noise** analysis of a **integrator** by hspice.Can the following sentence works it out?
.**noise** V(out) Is DEC 10 100 100Meg
and second a analysis result in the *.lis file,there are:
**** total output **noise** voltage = 3.2205m volts
**** total equivalent input (...)

Software Problems, Hints and Reviews :: 07-20-2004 13:41 :: alvays :: Replies: **0** :: Views: **1537**

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