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50 Threads found on edaboard.com: **Integrator Noise**

Why in RC **integrator** circuits , Caps are connected sometimes to supply voltage instead of ground ?

Analog Circuit Design :: 08-24-2016 15:48 :: Ltarek :: Replies: **5** :: Views: **551**

Thanks. One issue is that the output of the **integrator** is vdd or 0, since there is no dc feedback to control it, which gives a wrong simulation data.

Analog Circuit Design :: 05-27-2016 19:41 :: shanmei :: Replies: **7** :: Views: **2391**

Hi,
The signal and **noise** transfer function of a continuous time first-order delta sigma modulator using an simple active RC **integrator** both have a pole at 1/RC. The transfer functions are attached.115966
I was wondering, ideally, why can't we make RC very small, so the quantization **noise** is lower in the band of interest?

Analog Circuit Design :: 03-26-2015 23:57 :: raymond28j :: Replies: **0** :: Views: **555**

caps are used to act a a temporary or transient current shunt to **noise** voltage, the current is an **integrator** of voltage, also a DC block or RF coupler or an impedance vs f filter for bandwidth control.
There are millions of caps, with dozens of attributes, that define them uniquely.
pick 1 and ask for details with example schematic if that he

Elementary Electronic Questions :: 10-16-2014 19:34 :: SunnySkyguy :: Replies: **5** :: Views: **794**

Hi everyone,
Can someone suggest some papers or books or insight into the calculations for integrated vs. non-**integrator** **noise** components of a CTIA? I can't seem to find much of anything online...
Thanks in advance!

Analog Circuit Design :: 09-06-2014 00:27 :: koolposter :: Replies: **2** :: Views: **945**

103527Hi All,
I am studying the working of Delta Sigma(DS) and Incremental Delta Sigma ADCs. I am trying to implement those in Simulink. For DS I am getting proper output with **noise** shaping and good SNR. But when I am using the same structure for IDS with the reset connected to **integrator**, I am getting third and fifth harmonics

Analog Circuit Design :: 03-24-2014 07:16 :: karthikchanda :: Replies: **0** :: Views: **2042**

Hi all, I'm working on an optical sensor and am looking to increase my SNR. I've constructed a circuit to cancel out LED emitter **noise** with feedback control. PDref monitors just the emitter, while PDsig carries the sensor signal + emitter **noise**. Feedback consists of **integrator** -> JFET VCR -> current divider. Please see attached circuit. LT (...)

Analog Circuit Design :: 02-25-2014 23:38 :: RitchRock :: Replies: **0** :: Views: **575**

Hi, guy,
I need to design a large off-chip capacitor as the feedback capacitor of a on-chip current **integrator** for a large input current (over 10uA). However, I also need to use the same **integrator** to detection low level current (1pA). I know the input node Iin is very sensitive to **noise**. However, pad connection to (...)

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 12-12-2013 22:57 :: hyleeinhit :: Replies: **0** :: Views: **970**

Hi, I am doing a 3rd-order 2-bit CIFF DSM, I used Scherier's delta-sigma ToolBox to do the system design, ideally i can get 130dB SQNR with OSR=128. but i found the b1 and c1 coefficients are small so that the capacitors for the 1st stage **integrator** are very large when doing thermal **noise** budgeting. for this reason i increased the OSR to 256, this

Analog Circuit Design :: 12-01-2013 21:31 :: prcken :: Replies: **1** :: Views: **1360**

CIC uses modular arithmetic, overflow is by design. All CIC stages must have the minimal bitwidths according to CIC theory, then the output will be correct despite of **integrator** overflow.

Digital Signal Processing :: 07-29-2013 07:58 :: FvM :: Replies: **22** :: Views: **4883**

As said, low-pass transfer function is different from **integrator**, thus you get different **noise** shaping. You may want to calculate it using the Schreyer's popular Matlab toolbox or a different method of your choice.
First order SD **noise** shaping isn't mind blowing in any case, also the transfer function is at least similar to an (...)

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 04-16-2013 09:18 :: FvM :: Replies: **6** :: Views: **857**

Hi Jack,
A sigma delta modulator consists of one feedback loop around an **integrator** and a quantizer. This **integrator** (since you have 1/S therefore continuous) producing a low pass filtering of the input signal and a high pass filtering of the quantization **noise** which is injected at the quantizer, hense **noise** shaping the (...)

Digital communication :: 04-02-2013 12:49 :: jgk2004 :: Replies: **2** :: Views: **2963**

The **integrator** has to be reset at t=0 and read-out at t=8h. I don't think that you'll prefer an analog electronic timer implementation. If simple digital elecronic isn't acceptable for this design part, an electromechanical timer would be appropriate, I think.
As an additional comment, if you have problems to implement an accurate long time inte

Analog Circuit Design :: 03-02-2013 14:14 :: FvM :: Replies: **7** :: Views: **1204**

Hi Everyone. I am implementing a Kalman filter for an accelerometer. As you know,the accelerometer can be modeled as a Random Walk process and the output of a random walk process is assumed to be coming out of an **integrator** driven by white **noise**. This is described in "Random signals and applied kalman filtering, Brown,Hwang" chapter 2&5. The book

Digital Signal Processing :: 09-23-2012 23:35 :: sharpedge3 :: Replies: **0** :: Views: **1323**

Hi dinosaur !
And **integrator** can be used in many applications . for example converting an square wave to a triangle wave ( in SMPS or class D amplifiers or .... etc ) or perhaps as a funny wave shaper ! ( if you give a triangular wave to the input of an **integrator** you'll get something like a sine wave , but it is not pure ! ) and a differentiator

Analog Circuit Design :: 08-04-2012 21:42 :: goldsmith :: Replies: **4** :: Views: **3096**

75140
Inserted picture is the lossy-**integrator** in my circuit. To precisely run Simulink, I would like to calculate input referred **noise** for this lossy **integrator**, but I just don't know how to calculate.
Can anyone help me to calculate the input referred **noise** please?

Analog Circuit Design :: 05-30-2012 18:35 :: lawfulgm :: Replies: **6** :: Views: **1590**

So i do need to just make sure my maximum step size is small enough to do this integration correctly?
In a short, yes. You can review the datasheets of energy measurement chips, e.g. from Analog, that are all providing digital **integrator**s for di/dt sensors and check the implementation parameters.

Elementary Electronic Questions :: 02-28-2012 16:44 :: FvM :: Replies: **9** :: Views: **2613**

designing a Sigma delta 2nd order...CIFF architecture....
in literatures they hav suggested to use more linear and low **noise** first **integrator** for better they said first **integrator** is a power hungry one...
bt where the difference in design of low **noise** cum low power OTA and other OTAs lies... both (...)

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 09-14-2011 06:59 :: satyanitt :: Replies: **1** :: Views: **988**

HI ALL
i hesitated if this issue belong to this section but i will be very happy if some one of u will help me
i need to create sigma delta modulator for some application.
there is any section in the modulator that named **noise** shaping - it means that after oversampling signal we make **integrator** loops to the quantization **noise** and move (...)

Analog Circuit Design :: 08-27-2011 20:13 :: itmr :: Replies: **0** :: Views: **655**

Sinusoidal is ideal for this application.
In this case, a simple solution consists in an oscillator based on two integrating devices (double-intergrator oscillator, DIO).
Here, you have two outputs at the same time - with a phase difference of 90 deg.
In principle, you have several options:
One inverting (Miller-) inte

RF, Microwave, Antennas and Optics :: 06-21-2011 13:08 :: LvW :: Replies: **20** :: Views: **2745**

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supply 30a | bias network | vhdl dpll | wideband power amplifier | netlist synopsys | mmc command | gpio interface | setup margin | constrain timing | slew rate and comparator

supply 30a | bias network | vhdl dpll | wideband power amplifier | netlist synopsys | mmc command | gpio interface | setup margin | constrain timing | slew rate and comparator