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13 Threads found on Internal Timestep
Hi there, I an designing 10-bit pipeline ADC in HSPICe. It works good with ideal switches. However, when I replace the switches with the ideal one, face the following error: **error** internal timestep too small in transient analysis Does any one knows about the reason? Please kindly let me know about the reason. Thanks
Dear all In my transient analysis am getting this error. my input pulse is like PULSE (0 0.9 0 5N 5N 150N 300N) and my .tran 10N 500N UIC **error** internal timestep too small in transient analysis time = 0.80000E-11; delta = 0.37253E-22; numnit = 32168 1****** HSPICE -- C-2009.03-SP1 3
Hii, I'm getting the following error in cdesigner **error** internal timestep too small in transient analysis time = 0.61325E-06; delta = 0.25943E-14; numnit = 2658 I tried all the combinations in transient analysis and I tried it with increasing the stepsize also. But its of no use. Actu
Hi all, I am newly subscribed to this forum but I have been using this forum to obtain some useful infos about RF circuits for a long time. I have a problem using transient simulation in ADS. I am using VMMK-1225 PHEMT transistor of Avago technologies to implement a switch at 2 GHz. I give plus-minus 2 control voltage to the gate of my transisto
Hi All, I am using PSPICE and I am trying to get the HP Memristor model simulating. The SPICE Model is given in this paper: MemristorHPTest .SUBCKT modelmemristor plus minus PARAMS: +phio=0.95 Lm=0.0998 w1=0.1261 foff=3.5e-6 +ioff=115e-6 aoff=1.2 fon=40e-6 ion=8.9e-6 +aon=1.8 b=500e-
Sometimes HSPICE shows internal timestep error, like internal timestep is too small. It is caused by convergence problem. You can try other simulator like Spectre. Spectre's convergence is much better than HSPICE.
Hi, everybody! My error is : **error** internal timestep too small in transient analysis ... hspice diagnostic for nonconvergent nodes and elements
Hi! everybody, I simulate a frequency divider with the ADS transient simulator and also do the layout extraction with the momentum. However when I put the extraction data block (layout.sp) into the circuit in order to finish the post-layout simulation, the simulation/synthesis messages appear a error that shows "Error detected by hpeesofsim TRAN
Please tell me why the following error occured in Hspice? my circuit is a switched cap circuit. " **error**: internal timestep too small in transient analysis" Please answer me as soon as possible. Thanx Added after 2 hours 19 minutes: Can i increase the resolution of the analysis of Hspice?
**error** internal timestep too small in transient analysis time = 0.00000D+00; delta = 3.72529E-20; numnit = 304 I often encounter such error. How to deal with it usually?
Hey try and see if you are trying to ramp up your voltage sources too fast. internal time step algorithm is used by HSPICE to extrapolate to the next voltage or current. If there is a sudden ramp in the voltage or current in any node, then it will give an internal timestep error. Rather than changing GMINDC and G/C-SHUNT (which are used (...)
Decrease the internal timestep, what happed?
Use .options GSHUNT=1e-12 This will put a condutance of value GSHUNT in evry node to 0. "Conductance added from each node to ground. The default value is zero. Adding a small GSHUNT to each node can solve some ?internal timestep too small? problems caused by high frequency oscillations or by numerical noise. " Bastos