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Hello, I am currently learning about adc's and i could not find a proper and simple explanation of Folding and interpolation of adc's,can anyone guide me? Thank you in advance.

## sinc interpolation in fpga

For high sampling rate in Gs/s of scope passing data to fpga ,interpolation will be used , for a 8 bit adc , multiple and sum in sinc interpolation will result in 16 bit data . 255 pixel of lcd is representing 8 bit data,but after interpolation 16 bit is comes out , how to put this 16 bit into 8 bit "heights" ?

## FMCW sweep duration vs FFT spectrum/distance resolution

Hello! Let's assume that we have simple FMCW distance measurement system with linear frequency sweep from F1 to F2. Sweep duration is T. adc frequency is enough to digitize 128 points for each sweep duration T. Then we do some windowing and perform an FFT. For example 1024pt FFT (yes, i know about 128 points and interpolation, but it is from real

## S/H ciruit to cancell frequency multiplication in foldingADC

hi, I read the article that folding&interpolation adc facing frequency multiplication problem in adc processing. And S/H can eliminate this problem. Can anyone explain those ? Why frequency multiplicaiton happens ? and why S/H can eliminate it ? best

## How to solve zero crossing interpolation?

Hello, I have just simulated my folding and interpolating adc. The resolution of that adc is 8 bit with 1.4v full scale input. 1 LSB is about 5.5mV. After i simulated it staticaly(without frequency). The digital output only changed when Vin is 6.9mV or more. Theoritically it will changed at 5.5mV or more. Somehow i found that the zero-crossing m

## interpolation result of folding signals

hi, I have just done a DC sweep for my folding and interpolation adc. The top pane show the four folding signals generated by the four folding blocks. The below pane shows the 32 signals as a result of interpolation of the 4 folding signals. I have a problem that there are some wrong with the interpolated signalsat around 1.0 v of (...)

## value of interpolation resistors for Folding and ADC

Hallo, How to determine the value of interpolation resistors for Folding and interpolation adc? Thx in advance

## dspic30f2010 and saving the results of the ADC

hi i have a problem , i work with dspic30f2010 , i should convert an analog signal to digital so i use the adc of the dspic but after that i should treat the result of the conversion with a program of interpolation then transfer it with the can bus; my problem is that i read the datasheet, but i didn\'t find a solution , to do the program of inter

I designed 7bit Folding interpolation adc with 1.2V 65nm 1P6M process. and I'm going to prepare mesurment. I used input track and hold amplifier. this picture show measurement setup Why used 'Bias T' ??

## How to measure clockfeedthrough of an ADC and SCF

Hello friends, Can anyone tell me how to measure the Clockfeedthrough of an adc(Folding & interpolation) and A Switched Capacitor Low Pass Filter (5th Order Butterworth) Thanks in Advance Shady205

## Folding Interpolation ADC SNR problem

Hi Everyone, I have just designed a 8-bit folding interpolation adc. When I simulate my adc, I cannot get to 8-bit of resolution. The SNR that I got from the power spectrum is only -30dB. The noise level is at -40dB. Is there any technique I can use to lower the noise level in the adc. Can anyone who has experience with (...)

Hello all, I am now designing a clock driver for a folding interpolation adc. The output of the clock driver is connect to 32 comparators. The clock signal needs to be generated is 2GHz. Does anyone have experience with designing such a high speed clock driver?? Thanks for your help, chemaphy

## HELP: Clock driver circuit for Folding Interpolation ADC

Hello all, I am now designing a clock driver for a folding interpolation adc. The output of the clock driver is connect to 32 comparators. The clock signal needs to be generated is 2GHz. Does anyone have experience with designing such a high speed clock driver?? Thanks for your help, chemaphy

## a small query regarding sampling

Bandpass sampling is best approach to have reduced power consumptation for the adc implementation. I think most adc implementation independend from the architecture (Flash, Folding, interpolation, Multistage-Subranging,..) come down to about 150-500fJ/decisionstep. So a 10bit/1GS/s have (2^10-1)*1e9Hz*150fJ=153.5mW These results (...)