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26 Threads found on edaboard.com: Interview Verification
hi guys, I need your help. I have got an interview coming up with an asic company for frontend design position. I know VHDL quite well and also verilog. I have worked as a design/verification engineer for about a year and know about issues related to systhesis and simulation. but much of my experience has been working on fpga stuff. so please giv
I have an interview next week for this position. Any comments and advises are greatly appreciated. Description Design verification Engineer working on the next generation large VLSI to be used in continuously available hardware. You will start on an active team verifying a design in progress. You will migrate to the verification of (...)
Hi, This is a pretty common interview question. What is netlist simulation? After all why is it so essential part of design cycle? What do we acheive by doining netlist simulation? Cheers, Gold_kiss
hello evry body, my name is kranthi ,i am going to complete my MSc in soc design,presently i am working on MSc porject "memory controller verification using specman". could you plz inform me what type of questions generally they will ask on verification at interviews .. if u had any prvious question could you plz send me will be very h
Hi all, i've very humble request for all of you. ...actually i'm an ASIC/FPGA Design verification engineer and i have an interview with a company which does PCB/Board designs....I would really appreciate if anyone can give me what sort of questions are asked in interview related to PCB/Boeard Design. I dont have any resource other this (...)
hi, veterans please upload some good interview questions for ASIC\FPGA job hunters. I know there is another post on the same topic. But if anyone has more questions. Pleaseeeeee. help tnx