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26 Threads found on edaboard.com: Interview Verification
Hi everyone, I applied for a job as layout engineer. The job spec are the following: DUTY: -schematic to full custom layout translation -layout verification and DRC -floor planning for optimal die area -generation of wire bonding diagram for assembly approval before the tape-out REQUIREMENTS: -EE degree with focus on microelectronics -g
I am new for the layout. I was asked below question during the interview, "there are two seperate gnds for digital and analog, VSS-D and VSS-A, in the layout. how does the layout pass LVS and Calibra?" May I know how to approach it? Thanks in advance.
Hi i have one interview question.....? how you verify your mod10counter.....? how u write test cases and verification plan for u r mod10 counter.....? i need exact answer for this.......?
If I asked someone a design question, I would expect a broader solution 1st, because too many people get into implementation specific solutions before knowing what the assumptions are. Such as assumptions and specs. By asking the question at least clarifies what assumptions can be neglected. But design has many levels not just the basic function an
Hello, This is from Google:QUALCOMM interview Questions | Glassdoor Good Luck.
Hi All, I have a t'con with Sasken for verification Engineer. Though i have attended few interviews with other companies for the same post, i want to know in particular about Sasken. So anyone who have attended earlier or working for the same can help me in this. Thanks in Advance:-D
Since you are interviewing for a DV job, I would suggest brushing up on System Verilog and have a rough understanding of the verification methodology (choose one of VMM/OVM/UVM). Don't memorize it, just understand TLM, BFM, and what sorts of abstraction these methodology is designed to provide. Terry
i had an interview question about this and i really couldn't answer. i would really appreciate if somebody could tell me. the question is: why to use assertions in the design? what is their advantage and disadvantage? why to use assertions in verification? what is their advantage over plain testing and what is their disadvantage over plain te
Which one of these designs is most suited to use formal verification instead of simulation completely (not hybrid approach)? -Multipliers -MPEG Decoder -Arbiters -CPU The property "If a request is received, a grant will eventually be detected" is a: -Liveness Property -Safety Property -Don't know "Blackboxing" is to e
hi, I will be having a phone interview with intel for the poistion asic verification engineer. i am a fresh grad. Could you pls give me some ideas about what kind of question they will be asking me? Thanks
i am in IV year, ti is coming in my college, on what topic i should concentrate,please help me! my branch is e.c.e. Is it for VLSI? If so brush up Verilog/VHDL. If you have any higher level verification experience like E/SystemVerilog/PSL that will be a GREAT advantage. You may also consider our internship program at CV
Hello everybody, Yesterday I was interviewed @Intel. I got a question which I could not explain. Please help me with that : Given a 256-input NAND gate how many test cases are required to verify it and how much coverage it will give ? Do we need to run all 2^256 cases to get 100% coverage.
I think the interview meant to say the reference model instead of the BFM, which is suppose to predict the expected result out of the DUT. Two ways we can detect this problem. One is with code review and the other is to check the intent in the test itself and not completely rely on the reference model. For example, if the DUT is suppose to dro
What are the opportunities that are available in India for freshers in VLSI.. I find it very difficult to get interview call for any companies.. Please share any openings in any of the companies here..
Hello all, I have an interview with Synopsys for a AE position (AMBA product line). Can anybody tell me what do they look for. ? Also I need advice on AE positons in general. I have been working as a design engineer for almost 4 years both in RTL and verification. The experience has been decent, my questions ; 1. Is a transition to AE a good
Hello, I am looking for Question bank (along with answers) of FPGA. This is required for answering job interview questions. Pls help me. If any has such document for FPGA/ASIC/CPLD/VHDL/Verilog/verification, Please let me know the link to download or mail me to viswanatham1981@gmail.com Thanks, Vishwa
Hi, I will be facing interview for verification engineer job with a client. Can anybody please tell me what questions to expect and what are the answers. Thanks in advance
Hi, This Pdf contains lots of interview questions , might be useful : Link
Hi Veriguru, I think as a fresh graduate, it is not much use to prepare yourself to answer technical question related to the requirement of the job. I think it is more important to demostrate a good understand and interest in the projects and subjects you had done in the school. Of course, this also depend on how experience is the interviewers.
Hi, I came across a advertisment for hardware design eng. it says: 1. hardware/PCB design for RF applications, inc PA,ADC,DAC,BPF,antenna.. 2. RFIC performance test, bench verification and parametric characteristics. 3. antenna and indoor propagation analysis, FCC and EMC compliance testing. For no. 1 what interview question can i exp