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17 Threads found on edaboard.com: Issues Physical Design
Is this strictly a simulation or have you implemented your design in physical hardware? After only glancing at your code, two issues come to mind: 1. You got a code block define within main(), however there is no Superloop, i.e., while(1) associated with it. void main() { unsigned char msg = "Keyboard Test Program!\r\n"; unsigned ch
Hi I have started with cadence dtmf block pnr and following the lab .The problem is i am unable to address the issues .I need complete explanation what step to perform and what errors to fix at each stage ? the lab work is exclusively using gui its like fun play typing command and seeing the result.I need to address floorplanning,placement,cts,
Hi I have started with cadence dtmf block pnr and following the lab .The problem is i am unable to address the issues .I need complete explanation what step to perform and what errors to fix ?? how could i do that ?? the lab work is exclusively using gui its like fun play typing command and seeing the result.I need to address floorplanning issu
With respect to clock gate, what are various issues you faced at various stages in the physical design flow? plz anybody answe this question one more question for 2 year experience wat questions(topics) i can expect in interview apart from my project....
Simple, if you do not do physical design you will not have any chip in physical. Then no other domain will be there... Infact more PD engineers are required to solve the issues seen in 40nm and below.
In India or Tokyo, consultants are expensive than contractors. Reason is simple. Consultants need for specific issues, where as contractors are needed for normal execution of their own flow. In reality, Consultants are more knowledgeable than others (but some times, they are also dumb). As Per the first question : -Library development is
What actually happens in power planning? What are the library files invilved in it? How to optimise it? How are power rings,straps,trunks are designed? Howvdd & vss lines are laid? What are the issues encountered while placing i/o pads?
Please do provide some solutions for these queries as i need to know the solutions Somebody correct me if I am wrong... 1. What kind of issues or a report does a Backend physical design guy give to the Synthesis guy ones he has received the netlist. And what checklist should be done by th PD guy before starting off the flow.
Layout engineer lays the transistors using some tool considering the design issues. designer designs some circuit for specific application and he mentions some of the critical issues like matching and shielding. Layout engineer considers all these issues and lays a proper layout and (...)
You are in Hyderabad and having issues finding IC jobs? Even I may go to India after Masters :D Would be happy to build up a network of contacts in India and North America. Added after 3 minutes: whitchurch85, where is this list of companies?
Hi All, Can someone point to the kind of issues that the physical design team reports to the synthesis team, after the netlist is released to them for entire physical Flow. Thanks, Nik
What kind of issues can be faced while each physical design stage? And ways to overcome those issues?
What kind of issues can be faced while physical design in each step particularly in Floorplanning Placement CTS Routing And ways to overcome them?Or can any 1 suggest some good book on PD which explains each step in complete detail
Hi friends, In the era of low power design, I hope power plan is vital. I am interested to know the recommendations for best power plan? Would u pl list the issues that are possible at power plan stage in physical design? Pl post the issue and describe how it was solved. issues related to straps trunks (...)
Hi, design rules depends on lamba. The issues considered while shrinking are: Signal integrity: Synchronization and delays; Power consumption, leakage and the new physical phenomenon.
Hi, Can any one discuss the various issues with deep submicron physical design and the ways to tackle them... Please reply
Hi, I'm encountering the following issues.. in my implementaion phase. Tool Used :: Montery (dolphin) Question :: How is the placement grid computation done in any physical design tool 'm also pasting in a part of the log report to give you guys a clear idea. Stage :: Global Placement " Info