300 Threads found on edaboard.com: Latches
There are no asynchronous RAMs in an FPGA is that clear enough?
If you try to implement one it will either a) fail to implement, or b) end up as a huge design that implements latches in the LUT fabric to store bits.
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-08-2017 02:40 :: ads-ee :: Replies: 3 :: Views: 494
Hi - I'm working on fixing a pool controller and there are 2 pcbs that are connected by a flat ribbon cable (6 connectors). The male part easily pushes into the female. Then there is a small tab that fits over it that latches and adds the friction to squeeze the ribbon in.
I can take a picture but I've run into this problem of trying to locate
Hobby Circuits and Small Projects Problems :: 02-20-2017 23:53 :: DaveInPA :: Replies: 1 :: Views: 376
Yes - I recommend you avoid latches - using them is poor design practice. And using buffer is generally frowned on, especally when y is not even used as a buffer.
Also because you have a clocked process, using else to hold the state machine in the same state is not required, as this will happen automatically.
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-05-2017 21:43 :: TrickyDicky :: Replies: 27 :: Views: 2513
You have made this thread on at least 2 other forums. Your video did not work on those forums but it works here.
The datasheet for the receiver IC says that it latches an output when it receives the coded pulses and its MOD pin is high. The output pulses when it receives the coded pulses and its MOD pin is low.
Hobby Circuits and Small Projects Problems :: 12-24-2016 17:00 :: Audioguru :: Replies: 4 :: Views: 775
Quartus synthesizes the miso output register code because it can be rewritten as regular synchronous register description according to the template. Just pull-out rising_edge(clk).
There are however many latches generated and missing sensitivity list entries will probably cause simulation to synthesis mismatch.
Don't know why the design is wr
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-22-2016 13:59 :: FvM :: Replies: 4 :: Views: 1741
To convert the "simplified" example into something meaningful, there should be a first process line like
Reason: A combinational process should set the state of any affected signal in any conditional path and not generate latches. Signals working as state memory should be only set in clock edge sensitive processes.
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-21-2016 19:00 :: FvM :: Replies: 3 :: Views: 499
I merged the new post with your previous same topic thread, because the problem has been already discussed.
You are using a FSM template with a registered and a combinational process. As you already know, assigning a signal in the combinational process conditionally creates latches.
Question is what you want to achieve? Either the latch is un
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-03-2016 10:27 :: FvM :: Replies: 13 :: Views: 1215
What I get reported is that next_pause_lasting and next_pulse_lasting will be generated as latches because they are not in each of if/else branches, but I don't see how I could fix it.
This is because you have "null" in the else branch. Because you're not using a clock, or signals that behave like a clock, the FPGA
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-08-2016 13:25 :: TrickyDicky :: Replies: 6 :: Views: 862
Any way to extract a list containing all the latches used in a netlist (Sram macro) ? Does any simulator support this kind of functionality ?
ASIC Design Methodologies and Tools (Digital) :: 11-04-2016 05:26 :: vasaroopak :: Replies: 1 :: Views: 496
as per datasheet following programming of B port helps
CLRF PORTB ; Initialize PORTB by
; clearing output
; data latches
CLRF LATB ; Alternate method
; to clear output
; data latches
MOVLW 0Eh ; Set RB<4:0> as
MOVWF ADCON1 ; digital I/O pins
; (required if config bit
; PBADEN is set)
MOVLW 0CFh ; Value used to
; initialize data
Microcontrollers :: 09-11-2016 15:26 :: mvs sarma :: Replies: 3 :: Views: 521
You don't show read _s or pp_s in chipscope. I assume they are set to 1.
But this brings up another question, why are you using latches? There are no latches in an FPGA and have to be created with luts. They are prone to timing problems and will react to glitches on any signal. I highly recommend you do not use a latch.
PLD, SPLD, GAL, CPLD, FPGA Design :: 08-23-2016 05:57 :: TrickyDicky :: Replies: 5 :: Views: 383
I guess this link will help you understand better.
ASIC Design Methodologies and Tools (Digital) :: 08-21-2016 03:08 :: grvkpr18 :: Replies: 2 :: Views: 848
Cannot directly answer your question as I have never done STA on a latch based design.
In ASIC designing, within the design team, if you give a synth. design containing latches (which is not intended) the DfT engineer should be shouting back at you!
Better to fix such issues at the design stage and then go for STA and other ASIC design flows.
ASIC Design Methodologies and Tools (Digital) :: 05-30-2016 20:21 :: dpaul :: Replies: 6 :: Views: 575
Seems to refer to a 1:16 demux plus 16 RS-latches. Surely not available as a standard IC. You need to define a reset condition, by the way.
Digital Signal Processing :: 01-14-2016 15:24 :: FvM :: Replies: 6 :: Views: 786
thanks, but no pin 2 , if taken low, latches the chip off for good.
In the end , we have disabled it by jointly pulling LOAD pin low and discharging the SS cap with a BJT....we hope this is ok...datasheet doesn't tell.
Power Electronics :: 11-02-2015 20:38 :: treez :: Replies: 2 :: Views: 578
In usual terminology, a D-FF is an edge triggered device. Technically it's implemented as a combination of two latches, see the circuit from a HC74 datasheet.
The "DFF" shown in your post isn't edge triggered and can't work for a phase-frequency detector.
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 09-16-2015 06:37 :: FvM :: Replies: 8 :: Views: 667
I'm restricting my answer to the problem why ccstate bits are analysed as clocks. This happens because the combinational process generates latches for all signals that aren't assigned in every case. You'll find many warnngs about latch inference in the compilation report.
I'm not really motivated to dive into the design details and find out poss
PLD, SPLD, GAL, CPLD, FPGA Design :: 07-09-2015 09:12 :: FvM :: Replies: 6 :: Views: 668
What is the use of sr latches in the reciever electronic board of a laser land leveller?
Digital communication :: 06-27-2015 04:29 :: jaiswalkshitiz14 :: Replies: 0 :: Views: 354
As stated in the previous post you should use a latch instead of the 245.
The point of a 16 bit interface is for speed, would using a latch be any faster than writing 8 bits at a time without the latches? I don't think so!!
A trick that I used is to connect 10K resistors between the data lines ie 10k between D0 and D8 10K between D1 and D9 etc. Thi
Embedded Linux and Real-Time Operating Systems (RTOS) :: 05-25-2015 01:09 :: pjmelect :: Replies: 2 :: Views: 1225
Check your gate drive currents against TRIAC specs.
Top method has full voltage across opto driver , giving excess current blowing R9
While bottom should work with sufficient drive current at a <<10V then shuts off gate drive then TRIAC latches.
While for med/high drive the following is recommended
Power Electronics :: 03-17-2015 04:25 :: SunnySkyguy :: Replies: 2 :: Views: 1534