Search Engine

23 Threads found on Ldo And Phase Margin
ldo?. Ota?.
i'm a newbie and i'm designing ldo with Vin=3.5 V and Vout=3.1 V. I have a problem that when i simulate with Vin increase from 0V to 3.5V. If Vin increase from 0 to 3.5V in 5ms, vout is stably about 3.1 V.It's ok.(pic1). But if Vin increase from 0 to 3.5V in shorter range of time, about 500us, vout is not stabe,it oscillate.(pic 2) I (...)
in usual opamp ac simulation, the phase margin(PM) starts from 180-degree or 0-degree, and PM=phase (when VDB(out)=0) or 180+phase (when VDB(out)=0); however, in bandgap core loop ac simulation (using two bjt to generate detaVBE, and using an opamp to force V+ = V-), the (...)
Hi, I am currently debuging the Bandgap and ldos peaking at 3V power supply problem; please refer to the attachment 70540 the norminal VDD is 3.3V, and I look at the schematic, simulation results shows OK, no much variation with power supply change, also the phase margin of (...)
ldo load current source or resistive :The reality is some where in between ,so i would test ldo with both resistive and current source ,ofcouse you get different AC gain from the fact that current source has high output impedance . make sure you plot phase margin Vs load resistor
Hi,all For NMOS ldo, we usually thought it intrinsic stability. and I'm sure for high load, the ldo is stability. But how about light load, or no load? For that condition, the output shows a low frequency pole. So, there are two low frequency poles, and it's hard to make good phase margin. (...)
Hi, dear all: the figure is captured from a datasheet of ldo. and I find that most of ldo datasheet report the PSRR of 10~1M Hz, and the noise of 100~100k Hz. why these frequency range? the higher frequency is no need to care about? or the PSRR and noise is attenuated too much at higher frequency? (...)
The ldo under Iout=0 is unstable. Sometimes phase margin is not trustable.
I am designing an ldo that has an external load range from 1uF to 10uF. Under loaded conditons (current load), I have pretty good phase margin, however for the unloaded (current), my phase margin reduces significantly. I have tried incorporating a zero to offset the phase rolloff, however (...)
Hi, I inherited some ldo design from a "departed" designer, and since this is my first ldo design (I've done some simple regulators before, but not like this) I have some pretty basic questions. Here are the basic specs first: - the ldo is a step down from VIN=6.5V to VCC=5V (not much of an ldo really (...)
hi all, i need a mathematical relation ship between phase margin and load transient response of ldo.If anyone knows could you please post it . thanks If such a relationship exists in a closed mathematical form, it surely will depend on the order of the closed loop system. I know that such a relationship exists for
Hello everyone, could anyone tell me how to do the ac simulaion of ldo?I use an ideal current source as load. and I try to just simply break the feedback loop and measure the gain and phase of the ldo. But the power pmos transistor doesn't work in saturation region. So I don't think this (...)
Hi, all I am designing a ldo. But when I simulated the open loop gain and phase, I found that the dc gain, unity gain frequency and phase margin are different in different loading condition. How can I deal with it? Could you give me some suggestions? Thank you! Ken 2007/08/0.6
Hi penghan, i don't quite understand your point. if you think p1/p2 are always lower than 0dB, this is already a single pole transfer curve and no need zero to compensate. When we add output capacitor, there's extra pole above 0dB as this cap always big, so the Bode is 2-pole system and we need zero to compensate it, unless you have a (...)
From NSC's application note, Stable loops typically require a phase margin of >20° for ldo. But I think you need keep some margin in design.
how to simulation phase margin about ldo ? someone tell me , OPA only act as "DC" buffer don't care phase margin , In gerneral , I sim phase margin is refere to cmos circuit design layout & sim /baker use large R + C in feedback . and (...)
Hi I want to check the ldo that drive the inverters that take 1 mA. In AC analysis, to check the loop gain and phase margin,should i put resistor at the output to sink 1 mA or straight away the ldo output drive the inverters? I found out the result is different for both method.
hello The ldo consists simple OTA as an error amplifier and opamp as a buffer, but not in a unity configuration, but with a gain 10V/V. i need it, cause i have low vdd=1.3 and high threshold voltages. the buffer is to move second pole to higher frequencies. The problem is phase margin. I know that (...)
Dear All: I design a ldo. The phase margin at UGF (150kHz) is great than 50 but ldo's phase margin is less than 20 at 8.5kHz. Is it safe in the design ?
Dear neter, A phase margin of about 40 degrees is more than enough with the settling in a ldo with a switching load. It is mighty difficult to use a PMOS drop out transistor or a very low drop out and get a very high stability in a 60 degree phase margin. Also, ESR of the load capacitance (...)