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Ldo High Voltage

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52 Threads found on edaboard.com: Ldo High Voltage
Hi, I want to measure the output voltage of ldo voltage regulator circuit. However, the output ripple is very sharp, so I think it has high frequency components. My oscilloscope only supports up to 200MHz bandwidth, so I am worried about distortion from measurement. I can borrow high bandwidth (...)
100 mA is slightly beyond the capability of analog switch ICs, I would use a MOSFET H-bridge. Gate drive solution depends on the ldo voltage range.
So I have a single PLL pin that needs .9v and draws no more than 5ma of current. I don't want to waste a whole ldo just for such a small task, so i want to use the 1.8v output from an existing ldo and drop it down to .9v for this pin. What 2-3 low cost component count solution do I have for this problem? My first thoughts was I would just use a
Hi Guys, I've this question. I'm using a HDMI converter chip which convert from another display format to HDMI. For the core voltage which run at 1.2V , they specify quite a tight requirement on core power supply: 1.1-.13. I plan to use a fast transient ldo for this power supply since it's going to power the core cput which would have plenty o
I have a circuit that require 15Vdc, I used LMR62014 (1.6MHz) initially. The circuit run okay, except the noise a little high. so I put a LT1761 after LMR62014. Changed the LMR62014 Vout to 16vdc, and LT1761-byp to 15v. I notice the LT1761 Voutput has ripple triangular voltage, several hundred hertz, magnitude about several hundred millivolts
zeners are not efficient nor stable compared to bandgap reference diodes used in all ldo's (LM317 type and many others) Zeners must draw more than the worst case load to ensure when loaded there is still enough current to get past the knee in the zener. Then when no load, that current * voltage can lead to thermal problems for high (...)
Hi all: I am design a current mirror, and this circuit is used in a ldo, so the quiescent current needs to small. But I found the W/L of the high voltage MOS(NM5 and NM7) is big (20u/1.6u), so the NM5 and NM7 can't into the sat. region when the current is small (< 5uA). Could you give me some suggestion? (other structure or (...)
At first, let me say that it is always a bit "problematic" to explain in detail the working principle (and the dimensioning) of a circuit designed by somebody else. Nevertheless, here are some explanations: The ldo consists of two parts: A regulated amplifier Ar (FET & CFA) and a control loop (error amplifier Ae). * The amplifier Ar is
You can build a PMOS ldo that works within the input rails entirely, so long as you have enough negative Vgs (wrt VIN) to get the on resistance you need. A NMOS ldo requires a supply above output voltage (by a fair bit) so when dropout is actually low, you need a supply above VIN. There are NMOS ldos now, especially for the (...)
Hi all: I wish a OPA for a ldo and the OPA operation voltage is 5~20V. For high voltage, I use LDMOS to design the OPA, but I found there isn't have vdsat parameter in my pdk. Do you have any suggestion or solution to know the LDMOS is in saturation region or not? Thanks for your reply. mpig
Hi, My question is regarding charge-pump which is used to salvage current from RF signal to power an RFID circuit. My understanding is, because the current must continue to be available even when there is a small gap in the RF signal, the charge pump must charge its load capacitor up to a voltage which is higher than the normal VDD used for the r
If you are lazy, use a 3.3V ldo.
I presume that by ldo, you mean low dropout regulator? i would preceed it with a resistor with a decoupling capacitor to earth. Say 10 ohms and 470 MF. As a vehicle battery is extremely low impedance you have huge currents and induced voltages running wild to give such a large voltage spike. I would totally re-evaluate the connection of (...)
can any buddy tell me what is the role of load current specification in case of ldo, as ldo output is connected to another cmos block in mostly case to the gate of MOS so what the use of load current then as i guess prime requirement is only the voltage not current...any suggestion...please help me out
use a LC filter... close to ldo use decoupling caps near the pins as per the fpga vendor suggestion...
Hello I need to get ldo output voltage (Vout) high accuracy, how can I do? for example, the reference is bandgap voltage (vbg). 1, if vbg temperature coefficient(Ts) and accuracy are both poor, do I need to trim vbg accuracy? or the other? or both? then trim Vout ? 2, if vbg Ts is good, but accuracy is poor, do I (...)
Hi, all, I'm designing a ldo with high PSR of 75dB up to 100KHz. The input voltage is 3.5 and output is 3.3 with a max current of 300mA. Any suggestion on the topology of the ldo is welcomed. Thanks. Best Regards,
HI, I am new to ldo design. How to setup PSRR simulation in cadence for ldo? What are the general methods to improve PSRR of ldo ?
The idea that an ldo is high-efficient is false .. It can just tolerate low voltage difference between input and output .. Otherwise it behaves as any other linear voltage regulator .. One of the simplest options is to drop 2V by using 3 silicone diodes connected in series, but it can be done in one-hundred-and-one (...)
as long as it is a linear regulator , no difference in power consumption equation between an ldo and Non-ldo regs. ldos have an advantage of minimum input voltage requirement. srizbf 1stmay2010


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