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12 Threads found on edaboard.com: Ldo Miller
How and why does miller compensation affection the PSRR of an ldo?
This is always one of the struggles with a PMOS ldo. And try it with a PNP sometime. Any "groundward drag" on the final gate is miller amplified. And not attenuated like your explicit comp network. More shunt C from the final gate to VDD would maybe help, like replacing the miller comp with shunt comp. A big area hit perhaps, but maybe a (...)
Hi All, I have been working on the following architecture for a three stage ldo. 85731 This is a Three stage ldo with a single miller capacitance compensation using inverted current buffers. The first stage is a basic pmos input differential error amplifier. The second stage is like a unity gain buffer. The third s
Hey guys, I have a three-stage ldo. The simulation result is in attached (without compensation). Looks like the dominant pole is only about 19 Hz, the second pole is around 90 kHz. UGB freq = 640 kHz. The dominant pole is too low. And the DC gain is too high. I tried to do a miller compensation. It turns out the dominant pole moves t
i want to design a local ldo (with internal-chip CL)for pre-regulator for my one sub-module, the loading current is 20uA or so. then, what structure can i use? if i use miller two-stage opamp, can it be OK? and what value of CL should i use? 1pF can be OK? is there any suggestion? and what aspects should i consider in my ldo design? thanks all.
i have some questions need your help, some of these may be simple, but i want to discuss more deeply. 1, in HV process, i see an inverter like the following picture shows, the resistor may be 100K or some other value. what is the role of the resistor? and how it works? 79865 2, in two-stage mill
I am designing a ldo which can drive 50mA current, use a one stage op and a PMOS as output transistor, use internal 100pF cap as output capactor. When I do ac simulation, I find that the pole on OP's output is 18k, the output pole is 4M, and the phase margin is too small. i think the dominate pole should be the output pole, so how to compensate it
Dear transB: Thanks again for your help,I confirmed for your Q1 & Q2 And I can not find a RHP from the p/z mapping I posted for Q3, It does have effect to the zero, it shirt the zero about only one decade by varying the resr from 10m~1 ohm, so I think it not the domain factor to form the zero. Another bad news I want to tell you, T
I have design ldo voltage regulator for 1.5V regulated supply with output current max 40mA. But i have problem when i connect this ldo with my other chip module. it's giving oscilliatig regulated output with 1.5V voltage level.while i connect 0.1uF capacitor. i.e off chip it is working fine. the thing is that i cannot connect 0.1uF off chip.beacau
I'd say that the poles can be divided into two groups: -Poles in the opamp: miller pole and mirror pole (that should be the non-dominant one) -poles of the ldo: there are those cause by the opamp, the loading of the pass device on the opamp will create another pole, and output capacitance (C0) will add another pole as well.
I do not think that LDR has anything to do with a ligh dependent resistor. I think LDR is still the same good old ldo. I have seen some people from the East call it that way. Coming to the Dual loop feedback, instead of using a miller Capacitor, we tend to use two capacitors with one capacitor feeding back from the output stage . Since there is
can you upload IEEE paper robust frequency compensation scheme for ldo regulators or A capacitor-free cmos low-dropout regulator with damping-factor .. or Single miller Capacitor Frequency Compensation Technique for Low ... by the way , you make ldo by BJT or CMOS process Added after 2 minutes: